Stacked Memory Chip Pad Structure for Warping Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor storage devices face yield reduction due to warping issues caused by stress differences in the insulator and burying members, leading to potential short circuits and defects during manufacturing.
Innovation Solution
Incorporating high compressive or tensile stress burying members with internal stress values different from the insulator layers, strategically positioned to intersect with conductor layers and prevent warping, while simplifying the arrangement of connection pads for efficient bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulator layers and burying members are used in the semiconductor storage device, then electrical insulation and structural support are provided, but stress differences cause warping leading to short circuits and yield reduction
Solution Approach 1:
The patent applies the counterweight principle by introducing a burying member with stress value different from the insulator layer to compensate for and counteract the warping caused by stress differences. The burying member acts as a counterbalancing element that offsets the detrimental warping effects, thereby maintaining planarity and improving yield.
Solution Approach 2:
The patent changes the stress parameter of the structure by selecting materials with specific stress values for the burying member and insulator layer. By carefully controlling and adjusting the stress values of different layers, the patent achieves stress balance and prevents warping, thus resolving the contradiction between reliability and structural stability.
2Productivity
If connection pads are arranged in boundary regions, then bonding efficiency is improved, but stress concentration and warping risks increase
Solution Approach 1:
The patent applies local quality by differentiating the stress characteristics in different regions of the device. The burying member is strategically positioned in boundary regions where connection pads are located, providing localized stress compensation exactly where needed. This allows efficient bonding in boundary regions while preventing stress concentration and warping through the specially designed local stress distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces warping and defects, maintaining yield and ensuring reliable electrical connections between circuit and memory chips, thereby enhancing the manufacturing efficiency and quality of semiconductor storage devices.
Implementation Method 1
The first member has a stress value different from a stress value of the first insulator layer
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a first chip with a substrate and a second chip. The second chip has a memory cell array with wiring layers spaced apart from each other in a first direction and a memory pillar that penetrates the wiring layers in the first direction. Connection pads are in a boundary between the first and second chips. Contacts extend in the first direction from the connection pads. An insulator layer surrounds the contacts in a plane parallel to the substrate. A first member is adjacent to the insulator layer in the plane. The insulator layer separates the first member from the first contacts, and the first member has a stress value different from a stress value of the first insulator layer.