Memory System Page-Level Address Translation
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Solution Overview
Problem
In conventional NAND flash memory systems, managing address translation in blocks leads to slow random read/write speeds and fails when data in blocks intended for garbage collection becomes damaged, causing system failure due to inability to release blocks.
Innovation Solution
Implementing a memory system that manages address translation in pages, using a NAND controller with a comparison unit to compare physical and logical addresses, and an unknown page list to resolve errors and facilitate garbage collection efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If address translation is managed in blocks, then the system can maintain simple block-level management, but random read/write speed decreases because the whole block must be accessed even for small data
Solution Approach 1:
The patent segments the address translation management from block-level to page-level. Instead of managing the entire block as a single unit, the system divides it into smaller page units (e.g., 4KB pages within 256KB blocks). This allows random read/write operations to access only the specific page containing the data rather than the entire block, significantly improving access speed while maintaining manageable granularity through page-based translation tables.
2Speed
If address translation is managed in pages, then random read/write speed increases because only relevant pages need to be accessed, but the system complexity increases and garbage collection becomes necessary
Solution Approach 1:
The patent introduces a page management table as an intermediary data structure between the physical block and logical address space. This table stores mappings between logical addresses and physical page addresses, allowing the system to manage page-level granularity without directly handling the complexity of individual page operations. The intermediary table abstracts the complexity, enabling efficient page-level access while simplifying the overall management structure.
3Productivity
If garbage collection is performed to release blocks with unnecessary data, then block reuse efficiency improves, but system reliability decreases when data in blocks becomes damaged and cannot be read
Solution Approach 1:
The patent implements preliminary verification of data integrity before initiating garbage collection operations. The system checks whether data in candidate blocks can be successfully read and verified before attempting to relocate it. This preliminary action prevents garbage collection failures that would occur if damaged data were encountered during the relocation process, thereby maintaining system reliability while still enabling efficient block release when conditions are favorable.
Solution Approach 2:
The patent prepares alternative storage locations and verification mechanisms in advance to cushion against potential data read failures during garbage collection. By pre-allocating backup pages and establishing error detection protocols before the garbage collection process begins, the system can handle data damage scenarios without causing complete system failure, thus protecting reliability while maintaining productivity.
Data Source
AI summary
According to one embodiment, a memory system includes a nonvolatile memory, a storage unit, and a comparison unit. The nonvolatile memory stores an address translation table recording a first address and a second address corresponding to the first address and a write data. The storage unit stores a list and the address translation table. The list stores a third address. The address translation table is loaded from the nonvolatile memory in response to an access request to the nonvolatile memory. The address translation table includes the first address as a target of the access request. The comparison unit compares the third address stored in the list and the second address recorded in the address translation table and outputs a comparison result.