Nonvolatile Memory Page Address Notification
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Solution Overview
Problem
Conventional communication between NAND flash memory and controllers requires the controller to determine the program order for data write operations, leading to increased processing load and costs due to the need for various circuits and frequent development of new controllers to support different write methods and generations of NAND flash memories.
Innovation Solution
The nonvolatile memory device notifies the controller with a page address corresponding to the next program operation, allowing the controller to simplify data write operations without needing to recognize the specific program order, thereby reducing the processing load and enabling support for various write methods and generations of NAND flash memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the controller determines the program order for data write operations, then the data write operation can be completed, but the processing load and costs increase due to the need for various circuits and frequent development of new controllers
Solution Approach 1:
The nonvolatile memory device autonomously determines and executes the program order for data write operations without requiring the controller to specify the sequence. The memory device includes a control circuit that automatically manages the programming sequence of multiple pages, thereby reducing the controller's processing load and circuit complexity while maintaining full functionality.
2Adaptability or versatility
If the controller needs to support different write methods and generations of NAND flash memories, then compatibility is improved, but development costs and complexity increase
Solution Approach 1:
The nonvolatile memory device incorporates a control circuit that can automatically adapt to different write methods and memory generations. The control circuit is designed to handle various programming scenarios (sequential programming, interleaved programming, etc.) internally, making the memory device universally compatible with different controllers without requiring the controller to be updated for each memory generation or write method.
3Productivity
If the controller and nonvolatile memory have frequent communication processes, then data write operations can be performed, but communication time and power consumption increase
Solution Approach 1:
The controller issues a single preliminary command to initiate a batch of data write operations, and the nonvolatile memory device's control circuit automatically manages the subsequent programming sequence without requiring intermediate communications. This preliminary action approach reduces the number of communication cycles while maintaining high data write throughput, thereby reducing communication time and power consumption.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.