Memory Device Page Buffer Address Control for Read Latency
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Solution Overview
Problem
Current memory devices face performance limitations in read operations due to latency issues caused by error correction decoding and insufficient storage capacity, leading to delayed responses to read requests.
Innovation Solution
A memory device and method for operating a memory controller that includes a data output controller to select and control page buffers for data output, and an operation controller to monitor storage capacity and manage read data output by adjusting the page buffer address control signal, ensuring continuous data transfer without interruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If read data is sequentially output according to read enable signal, then data transfer efficiency is improved, but latency occurs when storage capacity is full
Solution Approach 1:
The memory controller pre-allocates storage space in the data buffer for read data before the actual read operation completes. This preliminary preparation ensures that when read data arrives sequentially, there is already designated storage space ready, preventing interruptions and reducing latency caused by storage capacity checks during data transfer.
Solution Approach 2:
The patent replaces the traditional mechanical/wait-based storage management with a signal-based control system. The page buffer address control signal dynamically manages the interface between the memory device and data buffer, allowing the system to anticipate storage needs and coordinate data transfer timing without physical interruptions or delays.
2Stability of the object's composition
If storage space is pre-allocated for read data, then data output continuity is improved, but storage capacity management complexity increases
Solution Approach 1:
The memory controller implements a feedback mechanism by monitoring the storage capacity of the data buffer and dynamically adjusting the page buffer address control signal accordingly. This feedback loop ensures continuous data output by anticipating storage needs and coordinating with the memory device to maintain stable data flow without interruptions.
Solution Approach 2:
The page buffer address control signal acts as an intermediary between the memory device and the data buffer. It mediates the data transfer process by managing the interface between these two components, coordinating timing and addressing to ensure continuous data output while simplifying the overall storage capacity management through centralized control.
Data Source
AI summary
The present technology relates to an electronic device. More specifically, the present technology relates to a memory device, a storage device, and a method of operating a memory controller. According to an embodiment, a memory device that outputs read data in response to a read enable signal provided from a memory controller includes a plurality of memory cells configured to store data, a plurality of page buffers configured to sense the data stored in the plurality of memory cells through a plurality of bit lines, and a data output controller configured to select a target page buffer to output data from among the plurality of page buffers according to a page buffer address control signal provided from the memory controller and control the selected target page buffer to output data stored in the selected target page buffer according to the read enable signal, while the read enable signal is input.