Semiconductor Memory Page Buffer Addressing Circuit
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in data storage and retrieval due to the complexity of bit line address signals and the need for separate address signals for odd and even bit lines, leading to increased circuit complexity and occupation area.
Innovation Solution
The semiconductor memory device incorporates a page buffer block with sub-page buffer blocks arranged in a bit line direction, featuring page buffer selection units that selectively couple page buffers to common internal data lines in response to bit line address signals, reducing the number of address signal lines required and optimizing circuit layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate address signals are used for odd and even bit lines, then bit line addressing can be performed, but the number of address signal lines increases and circuit complexity increases
Solution Approach 1:
The patent combines odd and even bit line address signals into a single shared address signal line. The page buffer selection units use this shared signal along with sub-page buffer block selection signals to selectively couple specific page buffers to the common internal data line, thereby addressing both odd and even bit lines without requiring separate address signal lines for each.
2Ease of operation
If separate address signals are used for odd and even bit lines, then complete bit line addressing is achieved, but the occupation area of the page buffer unit increases
Solution Approach 1:
The patent merges the address signal lines for odd and even bit lines into a single shared line, directly reducing the occupation area of the page buffer unit by eliminating redundant signal lines while maintaining full addressing capability through the sub-page buffer block selection mechanism.
3Adaptability or versatility
If complex addressing schemes are used to address all bit lines, then complete addressing coverage is achieved, but the number of address signal lines increases
Solution Approach 1:
The patent segments the bit lines into sub-page buffer blocks (odd and even blocks) that can be independently selected. By combining sub-page buffer block selection signals with the shared address signal, the system achieves complete addressing coverage for all bit lines while using fewer address signal lines than traditional approaches.
4Productivity
If traditional page buffer configurations are used, then data storage and retrieval can be performed, but the circuit layout is complex and occupation area is large
Solution Approach 1:
The patent merges multiple page buffers into sub-page buffer blocks with shared address signal lines and a common internal data line. This consolidation maintains data storage and retrieval efficiency while reducing the occupation area by eliminating redundant circuit elements and optimizing the layout.
Data Source
AI summary
A semiconductor memory device may include: a memory cell array having a plurality of memory cells, a plurality of word lines and a plurality of bit lines; a page buffer block including N number of sub page buffer blocks which are arranged in a bit line direction and each of which includes a plurality of page buffers arranged in a word line direction and a bit line direction; common internal data lines respectively corresponding to the sub page buffer blocks; and a page buffer decoder including page buffer selection units which are electrically coupled between the page buffers included in each sub page buffer block and a common internal data line corresponding to the sub page buffer block and which electrically couple the page buffers included in the sub page buffer block selectively to the common internal data line.