Nonvolatile Memory Page Buffer Bit Line Control
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Solution Overview
Problem
Nonvolatile memory devices face challenges in efficiently sensing on-cell and off-cell states, particularly in reducing the time required to sense data stored in memory cells while maintaining accuracy.
Innovation Solution
The implementation of a nonvolatile memory device with a memory cell array, page buffers, and a control logic circuit that transmits bit line setup and shutoff signals to precharge and shutoff circuits, allowing for controlled transition times based on the gradient of the bit line shutoff signal, enabling simultaneous precharge and developing operations to enhance sensing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bit line setup signal transitions quickly to reduce sensing time, then read operation speed is improved, but the precharge operation may not complete sufficiently, reducing sensing accuracy
Solution Approach 1:
The patent applies dynamics by making the transition time of the bit line setup signal variable rather than fixed. The control logic circuit dynamically adjusts the transition time based on the gradient of the bit line shutoff signal, allowing the system to optimize between precharge completion and read speed for different operating conditions.
Solution Approach 2:
The patent changes the parameter of transition time of the bit line setup signal according to the gradient of the bit line shutoff signal. By varying this temporal parameter dynamically, the system achieves sufficient precharge for accuracy while maintaining high read speeds when conditions permit.
2Loss of time
If the bit line shutoff signal gradient is increased to improve sensing speed, then read operation time is reduced, but the control complexity increases
Solution Approach 1:
The control logic circuit incorporates feedback by monitoring the gradient of the bit line shutoff signal and using this information to adjust the transition time of the bit line setup signal. This closed-loop control allows the system to automatically optimize sensing performance without requiring complex manual configuration.
Solution Approach 2:
The system performs self-optimization by having the control logic circuit automatically adjust timing parameters based on the observed gradient of the shutoff signal. The system serves itself by using the shutoff signal's own characteristics to determine the optimal setup signal transition timing.
Data Source
AI summary
A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.