Memory Page Buffer Circuit with Temporary Storage Node for Program Time Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices face inefficiencies in data storage operations due to the time-consuming process of repeatedly applying program and verify steps, which can prolong the total program time.
Innovation Solution
A memory device with a page buffer circuit that includes a temporary storage node and a control logic circuit to selectively precharge bit lines based on target state information, allowing concurrent or parallel execution of dump and precharge operations, thereby reducing the total program time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the flash memory device repeatedly performs program and verify steps to store data in memory cells, then the data storage reliability is improved, but the total program time increases
Solution Approach 1:
The patent applies preliminary action by precharging the bit line before the verify step is completed. The control logic circuit determines the precharge condition based on the current verify result and target state, and initiates the bit line precharge operation in advance. This allows the next verify step to start immediately without waiting for the bit line to be fully charged, thereby reducing the total program time while maintaining data storage reliability through the repeated program-verify process
2Device complexity
If the flash memory device performs sequential program and verify operations, then the operation control is simplified, but the data storage efficiency decreases
Solution Approach 1:
The patent applies dynamics by making the operation mode flexible and adaptive. The control logic circuit dynamically switches between sequential operation mode and overlapping operation mode based on real-time conditions. When the verify result meets the target state or precharge conditions are satisfied, the system transitions to overlapping mode where bit line precharge is initiated during the verify step. This dynamic adjustment optimizes data storage efficiency without significantly increasing operation control complexity
Solution Approach 2:
The patent applies continuity of useful action by eliminating idle time between the verify step and the next program step. Instead of waiting for the verify operation to fully complete before starting bit line precharge, the system initiates the precharge operation as soon as conditions are met, ensuring that useful actions (verify and precharge) overlap and continue without interruption. This maximizes data storage efficiency by keeping the system continuously productive
Data Source
AI summary
Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.