Nonvolatile Memory Page Buffer Circuit Pre-Charge Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory devices face inefficiencies in program verification due to prolonged pre-charge times caused by coupling capacitance among bit lines during read operations, which hinder program efficiency.
Innovation Solution
A nonvolatile memory device with a page buffer circuit and control logic that selectively pre-charges bit lines during read and verification read operations, adjusting pre-charge times based on the number of selected bit lines, program loops, or target program states to reduce coupling capacitance and shorten verification times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a pre-charge voltage is applied to all bit lines during a read operation to compensate for coupling capacitance, then sensing accuracy is improved, but pre-charge time increases
Solution Approach 1:
The patent applies pre-charge voltage selectively to only those bit lines that are actually selected for the read operation, rather than pre-charging all bit lines. This localized approach maintains sufficient sensing accuracy for the selected bit lines while avoiding the time penalty of pre-charging the entire bit line array, thus resolving the contradiction between sensing accuracy and pre-charge time.
Solution Approach 2:
The patent dynamically adjusts the pre-charge time based on the number of selected bit lines. When fewer bit lines are selected, the pre-charge time is reduced accordingly. This dynamic adaptation allows the system to maintain sensing accuracy when needed while minimizing pre-charge time when fewer resources are required, effectively resolving the time-accuracy tradeoff.
2Ease of operation
If a fixed pre-charge time is used for verification read operations, then operation simplicity is maintained, but program efficiency deteriorates due to prolonged verification time
Solution Approach 1:
The patent introduces dynamic pre-charge time adjustment for verification read operations based on the number of selected bit lines. The control logic automatically determines the appropriate pre-charge time according to the actual verification needs, which maintains operational simplicity from the user perspective while significantly improving program efficiency by avoiding unnecessary long pre-charge times.
Solution Approach 2:
The patent changes the pre-charge time parameter dynamically based on the verification operation requirements. By adjusting this critical timing parameter according to the number of selected bit lines, the system achieves both operational simplicity (automatic adjustment) and improved program efficiency (optimized timing), resolving the contradiction between these two features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves program efficiency by reducing program verification time and compensating for sensing noise, thereby enhancing the overall performance of nonvolatile memory devices.
Implementation Method 1
prolonged pre-charge times caused by coupling capacitance among bit lines during read operations
Data Source
AI summary
A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and configured to selectively pre-charge the plurality of bit lines, and control logic configured to control the page buffer circuit such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a first time at a read operation and such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a second time different from the first time at a verification read operation. The second time is determined on the basis of the number of selected bit lines of the plurality of bit lines at the verification read operation.