Memory Page Buffer Control Logic for Flexible Data Output Order
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Solution Overview
Problem
Memory devices face challenges in adapting their data output to various operating environments, leading to potential inaccuracies in data readings by memory controllers due to inconsistent data handling.
Innovation Solution
A memory device with a memory cell array and page buffer circuit, including control logic that manages the output of hard decision data and soft decision data by storing and dumping them between latches, allowing for flexible data output modes based on commands from the memory controller, ensuring accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory device outputs hard decision data and soft decision data in a fixed order, then the data output structure is simple, but the memory controller cannot adapt to various operating environments leading to inaccurate data readings
Solution Approach 1:
The patent implements dynamic data output control by allowing the memory device to switch between different output modes (first output mode where hard decision data is output first, and second output mode where soft decision data is output first) based on commands from the memory controller. This dynamic adaptability resolves the contradiction by enabling the system to adjust its behavior according to operating requirements without requiring a completely complex redesign of the data output structure.
Solution Approach 2:
The patent changes the output order parameter of data by introducing mode setting mechanisms that allow switching between different output sequences. The control logic modifies the data output parameters based on the operating environment and controller requirements, enabling adaptation while maintaining a relatively simple base structure that only needs to implement the switching capability.
2Measurement precision
If the memory device uses multiple latches for storing hard and soft decision data, then data accuracy and adaptability are improved, but the device complexity increases
Solution Approach 1:
The patent segments the data storage function by using separate latches for different data types within the page buffer circuit. Specifically, it uses a first latch for hard decision data and a second latch for soft decision data. This segmentation allows the system to maintain high data accuracy by properly separating and handling different data types while keeping the overall structure modular and manageable.
Solution Approach 2:
The page buffer circuit is designed with multi-functionality to handle both hard decision data and soft decision data storage and transfer operations. The control logic within the page buffer performs multiple functions including storing data in different latches, dumping data to memory cells, and controlling the output sequence based on mode settings. This universal design improves data accuracy while avoiding the need for completely separate dedicated circuits for each function.
3Adaptability or versatility
If the memory device stores and dumps data between latches during read operations, then data output flexibility and accuracy are improved, but the read operation time increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring the page buffer circuit with multiple latches and control logic that are ready to perform data dumping operations. The control logic is pre-programmed with mode settings that determine the data output sequence before the actual read operation begins. This allows the data to be prepared and positioned in the appropriate latches during or after the read operation, reducing the overall time penalty by having the infrastructure ready in advance.
Data Source
AI summary
A memory device including: a memory cell array including pages each page including memory cells; a page buffer circuit including page buffers corresponding to the memory cells of each page, each of the page buffers including first through N-th latches; and a control logic to control first hard decision data and first soft decision data read in a first read operation on a first page to remain in a first page buffer during a second read operation on a second page, and control an output operation such that the first hard decision data is output after the first soft decision data is output when the memory device is set to a first output mode, wherein the first hard decision data is based on a normal read level and the first soft decision data is based on an offset read level read from the first page.