Nonvolatile Memory Page Buffer Data Line Load Reduction
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Solution Overview
Problem
Nonvolatile memory devices face challenges in reducing the load on data lines, which affects operational performance and integration, particularly due to the narrow width of bit lines and data lines, leading to increased dump time and complexity in manufacturing.
Innovation Solution
The design includes a nonvolatile memory device with a page buffer circuit that features high-voltage and low-voltage circuits, along with latch circuits, sequentially arranged on a substrate, where the data lines are wider than the bit lines, reducing the load on data lines and improving operational performance by minimizing the need for additional latch circuits and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the width of data lines is reduced to increase integration density, then the integration density is improved, but the load on data lines increases and dump time increases
Solution Approach 1:
The page buffer circuit is divided into distinct functional regions: high-voltage circuit region, low-voltage circuit region, and latch circuit region. This segmentation allows data lines to be positioned in the latch circuit region where they can maintain adequate width for low load, while bit lines are routed through the high-voltage and low-voltage circuit regions where space is more constrained. The segmentation resolves the contradiction by spatially separating the requirements for data line width and integration density.
Solution Approach 2:
The patent utilizes vertical stacking of functional regions on the substrate to achieve high integration density without compromising data line dimensions. By arranging the high-voltage circuit, low-voltage circuit, and latch circuit in sequential regions along one dimension (away from the memory cell array), the design maintains adequate data line width in the lateral dimension while achieving compact integration through vertical arrangement. This dimensional approach allows wide data lines to coexist with high integration density.
2Reliability
If additional latch circuits are added to reduce data line load, then the data line load is reduced, but the device complexity and manufacturing complexity increase
Solution Approach 1:
The patent combines multiple functions into the existing latch circuit region: data latching, data line termination, and output buffering. By positioning the latch circuits in a dedicated region with adequate space, the design achieves effective data line load reduction without adding excessive complexity. The merged functions are implemented within the structural framework already established by the regional division, avoiding the need for separate additional circuits for each function.
3Reliability
If data lines are made wider to reduce load, then the data line load is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies different line width specifications to different types of conductors based on their functional requirements. Data lines are made wider in the latch circuit region where low load is critical for reliable data output, while bit lines maintain narrower widths appropriate for their high-speed switching function. This local differentiation of quality allows the design to optimize data line load reduction without unnecessarily increasing manufacturing precision requirements across the entire device, as each conductor type receives the specific width treatment it requires.
Data Source
AI summary
A nonvolatile memory device according to some embodiments of the inventive concepts may include a memory cell array, a first page buffer connected to the memory cell array via a first plurality of bit lines, and a second page buffer connected to the memory cell array via a second plurality of bit lines. The first page buffer circuit may include a first bit line selection circuit, a first bit line shut-off circuit, and a first latch circuit. The second page buffer may include a second bit line selection circuit, a second bit line shut-off circuit, and a second latch circuit. The first and second bit line selection circuits, the first and second bit line shut-off circuits, and the first and second latch circuits may be sequentially arranged in a direction away from the memory cell array. A width of the data lines may be greater than a width of the bit lines.