Memory Device Page Buffer Bit Line Discharge Timing
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Solution Overview
Problem
Current memory devices face inefficiencies in programming and verify operations due to voltage coupling effects during precharge, which degrade the performance of bit line precharge during verify operations.
Innovation Solution
The implementation of a memory device with page buffers that include a latch and a bit line controller, where the bit line is discharged during the latch setting operation and precharged after completion, improving the performance of bit line precharge during verify operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bit line is precharged during verify operations, then the read speed is improved, but voltage coupling effects degrade the precharge performance
Solution Approach 1:
The patent applies preliminary action by discharging the bit line before the verify operation and precharging it after the latch setting operation completes. This timing arrangement ensures that the bit line is in the optimal state for each operation phase, avoiding voltage coupling effects during critical precharge operations while maintaining high read speed performance.
Solution Approach 2:
The patent implements dynamic control of the bit line voltage state by selectively discharging and precharging the bit line based on the operation phase. The bit line controller dynamically adjusts the bit line voltage to be discharged during latch setting and precharged during verify operations, optimizing performance for each phase while avoiding the degradation caused by static voltage coupling effects.
2Productivity
If the latch setting operation is performed during verify operation, then the programming efficiency is improved, but the bit line voltage interference increases
Solution Approach 1:
The patent extracts the harmful voltage coupling effect by introducing a bit line controller that actively manages bit line voltage during the latch setting operation. The controller discharges the bit line during latch setting to remove the voltage interference that would otherwise affect the verify operation, while still allowing the latch setting operation to proceed and improve programming efficiency.
3Speed
If the bit line is precharged too early, then the read speed is improved, but the voltage coupling effect degrades the precharge operation
Solution Approach 1:
The patent applies preliminary action by precharging the bit line after the latch setting operation completes rather than before. This timing ensures that the precharge operation occurs when voltage coupling effects are minimized, making the precharge operation easier and more reliable while still maintaining high read speed by having the bit line ready for the verify operation.
Data Source
AI summary
A memory device having improved performance includes: a plurality of memory cells programmed to one of a plurality of program states divided based on a threshold voltage; and a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines. Each of the plurality of page buffers includes a latch for storing data sensed from a corresponding bit line among the plurality of bit lines, and discharges the corresponding bit line while performing a latch setting operation including setting data stored in the latch in a verify operation on the plurality of program states.