Nonvolatile Memory Page Buffer Dumping Operations
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nonvolatile memory devices face inefficiencies in programming and reading operations due to structural differences between two-dimensional and three-dimensional memory devices, leading to increased operation times and resource utilization.
Innovation Solution
The implementation of an operating method for nonvolatile memory devices that utilizes first and second page buffers connected through bitlines, performing sequential input and dumping operations to optimize data transfer and storage within a memory cell array, allowing for efficient programming and reading of data across multiple pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential input operations are performed for multiple sub-pages, then data transfer completeness is improved, but operation time increases
Solution Approach 1:
The patent performs dumping operations in advance during ongoing input operations. Specifically, while the second sub-page data is being input to the second page buffer, the first dumping operation transfers data from the first cache latch to the first data latch. This preliminary action ensures data is prepared for subsequent programming without waiting for all input operations to complete, thereby reducing total operation time while maintaining data completeness.
Solution Approach 2:
The patent enables continuous data handling by overlapping input operations with dumping operations. Multiple page buffers operate simultaneously - some receiving new sub-page data while others perform dumping operations. This continuity eliminates idle states where page buffers would otherwise wait, maintaining productive action throughout the entire data transfer process and reducing overall operation time.
2Productivity
If multiple page buffers operate simultaneously, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent divides the page buffer system into multiple independent units (first page buffer, second page buffer, etc.), each with its own cache latches and data latches. This segmentation allows simultaneous operation of multiple buffers without interference, improving productivity. The modular structure manages complexity by making each buffer unit self-contained and independently controllable through standardized operations.
Solution Approach 2:
The patent implements universal page buffer structures where each buffer can perform both input operations (receiving sub-page data) and dumping operations (transferring data to latches) independently and simultaneously. This multi-functionality allows the system to handle multiple data pages through different buffers at the same time, significantly improving productivity while managing complexity through standardized, repeatable operations across all buffers.
Data Source
AI summary
A nonvolatile memory device includes a mat including a plurality of memory blocks, an address decoder configured to select one of the memory blocks in response to an address, an input/output circuit including first and second page buffers configured to program a plurality of data pages into a single physical page of the selected one of the memory blocks or store the plurality of data pages read from the single physical page of the selected one of the memory blocks, and a control logic configured to perform a dumping operation at an other one of the first page buffers and second page buffers when a data input operation or a data output operation is performed at one of the first and second page buffers of the input/output circuit. The input/output circuit includes a plurality of page buffers. The plurality of page buffers include the first and second page buffers.