Nonvolatile Memory Page Buffer Error Correction Logic
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Solution Overview
Problem
Nonvolatile memory devices face reliability issues during data read operations due to errors caused by shifting threshold voltages of memory cells, leading to uncertainty in determining the original data state and inefficiencies in error correction, especially when the number of errors exceeds the capacity of error correction codes.
Innovation Solution
The implementation of a nonvolatile memory device with a page buffer unit that includes latches for storing logic operation results and flag information to classify page buffers, perform XOR operations, and determine error occurrence, allowing for multiple read operations with varying voltages to correct errors based on the number of bits that can be corrected, thereby improving error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the read voltage is lowered to reduce errors in memory cells with shifted threshold voltages, then the number of errors can be reduced, but it becomes impossible to determine whether the original data state was '0' or '1' due to uncertainty in threshold voltage shifts
Solution Approach 1:
The patent performs a first read operation using an initial read voltage before the threshold voltage shift occurs (or before it becomes significant) to capture the original data state. This preliminary action stores the original state information that can later be used for accurate error correction, even when subsequent reads at lowered voltages cannot determine the original state.
Solution Approach 2:
The patent introduces an intermediary mechanism (the first read operation at initial voltage) that captures and preserves the original data state information. This intermediary step acts as a bridge between the original data storage state and the error correction process, allowing the system to determine whether threshold voltage shifts occurred without directly relying on the ambiguous lowered-voltage reads.
2Reliability
If error correction codes are used to correct data bits, then errors can be corrected when the number of errors is within a predetermined limit, but the ECC circuit occupies a wide area when configuring the nonvolatile memory device
Solution Approach 1:
The patent segments the error correction process into multiple stages: first determining the original data state through a preliminary read operation, then using this information to guide targeted error correction. This segmentation allows for more efficient error correction with reduced circuit requirements compared to comprehensive ECC circuits that must handle all possible error scenarios.
Solution Approach 2:
The patent changes the parameter of read voltage dynamically - using an initial read voltage for the first read operation to capture original states, then potentially using lowered voltages for subsequent operations. This parameter change enables a more efficient error correction approach that reduces the need for extensive ECC circuitry by leveraging voltage-dependent read characteristics.
3Reliability
If multiple read operations with varying voltages are performed to correct errors, then data integrity can be improved, but the operation time and complexity increase
Solution Approach 1:
The patent performs a preliminary first read operation using an initial read voltage to capture the original data state before performing subsequent read operations at lowered voltages. This preliminary action enables targeted error correction by providing baseline information, reducing the need for extensive multiple read operations and associated timing overhead.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array configured to comprise memory cells coupled by bit lines and word lines, a page buffer unit configured to comprise page buffers and flag latches, wherein the page buffers, coupled to one or more of the bit lines, each are configured to comprise a plurality of latches for storing logic operation results for error correction and configured to store data read using a read voltage, and the flag latches each are configured to classify the page buffers into some page buffer groups each having a predetermined number and to store flag information indicating whether an error has occurred in each group, and an error detection code (EDC) checker configured to determine whether an error has occurred in each of the page buffer groups.