Memory Page Buffer Initialization via Simultaneous Address Loading

Solution Overview

Problem

Current memory systems face inefficiencies in initializing the page buffer unit, leading to increased operation time and peak current consumption during data operations.

Innovation Solution

A memory system and method that simultaneously initialize the page buffer unit upon receiving an address command, utilizing control signals to optimize the initialization process, thereby reducing operation time and preventing peak current increases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the page buffer unit is initialized sequentially after address loading, then the initialization process is simple to control, but the operation time increases

Engineering Contradiction:

Improveinitialization control complexityVSAvoidpage buffer initialization time

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by initializing the page buffer unit simultaneously with the address loading process rather than sequentially after address loading completes. The control logic initiates the initialization operation at the same time the address is being loaded into the address buffer, overlapping these two operations to reduce total execution time without adding significant control complexity.

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If the page buffer unit is initialized simultaneously with address loading, then the operation time is reduced, but the peak current increases

Engineering Contradiction:

Improvepage buffer initialization timeVSAvoidpeak current consumption

Core Design Contradiction:

Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by selectively initializing only the necessary portions of the page buffer unit during the address loading process, rather than initializing the entire buffer simultaneously. The control logic determines which page buffer units need initialization based on the address being loaded and only activates those specific units, reducing the overall current consumption while still achieving time reduction compared to sequential initialization.

Inventive Principle:

Principle #16Partial or excessive action

3Use of energy by moving object

If the page buffer unit is initialized sequentially after address loading, then the peak current is lower, but the operation time increases

Engineering Contradiction:

Improvepeak current consumptionVSAvoidpage buffer initialization time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent applies preliminary action by initializing the page buffer unit simultaneously with the address loading process rather than sequentially after address loading completes. The control logic initiates the initialization operation at the same time the address is being loaded into the address buffer, overlapping these two operations to reduce total execution time without adding significant control complexity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies partial action by selectively initializing only the necessary portions of the page buffer unit during the address loading process, rather than initializing the entire buffer simultaneously. The control logic determines which page buffer units need initialization based on the address being loaded and only activates those specific units, reducing the overall current consumption while still achieving time reduction compared to sequential initialization.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS10283174B2Memory system initializing page buffers and operating method thereof

Publication Date: 2019.05.07 SK HYNIX INC

AI summary

A memory system includes a memory device for storing data, and a controller for controlling the memory device by outputting control signals to the memory device. In the memory device, when an address of a selected operation is received in response to the control signals, the memory device simultaneously initializes a page buffer included in the memory device.