Semiconductor Memory Page Buffer Program Interference Compensation
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Solution Overview
Problem
In NAND flash memory devices, the increasing integration of memory cells leads to a program interference phenomenon, causing threshold voltage shifts in even pages during programming, which results in widened threshold voltage distributions and potential data reading errors.
Innovation Solution
The semiconductor memory device employs page buffers and a controller to detect and adjust the threshold voltages of even memory cells by monitoring the voltages of adjacent odd memory cells, controlling the read operation conditions to mitigate the program interference effect and improve data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration is increased to narrow the interval between memory cells, then the memory density is improved, but a program interference phenomenon is generated causing threshold voltage shifts
Solution Approach 1:
The patent applies preliminary action by performing a read operation on adjacent odd memory cells before reading even memory cells. This preliminary detection of odd cell states allows the system to predict threshold voltage shifts in even cells due to program interference, and adjust read conditions in advance to compensate for these shifts, thereby maintaining reliability despite high integration density
2Productivity
If the even page program operation is performed earlier than the odd page program operation, then the program operation sequence is simplified, but the threshold voltages of even memory cells are greatly shifted due to program interference
Solution Approach 1:
The patent implements feedback by using the detected threshold voltage states of odd memory cells to adjust the read operation conditions for even memory cells. The system feeds back information about program interference effects (detected through odd cell readings) to modify subsequent even cell read operations, thereby compensating for threshold voltage shifts and narrowing the threshold voltage distribution despite the simplified program sequence
3Speed
If the threshold voltage distribution is widened due to program interference, then the program operation is faster, but errors occur in reading data
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting read operation parameters (such as read voltage levels or sensing thresholds) based on the detected threshold voltage shifts in odd memory cells. This adaptive parameter adjustment compensates for the widened threshold voltage distribution caused by program interference, maintaining data reading accuracy while preserving fast program operation speeds
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach predicts and compensates for threshold voltage shifts in even memory cells, enhancing the reliability of output data by adjusting read operation conditions based on detected voltage shifts, thereby reducing errors in data reading.
Implementation Method 1
detecting a shift in the voltage of the second even bit line due to a capacitance coupling phenomenon according to a shift in the voltage of the first odd bit line
Data Source
AI summary
A semiconductor memory device according to an aspect of the present disclosure includes a first page buffer coupled to a first even bit line and a first odd bit line, a second page buffer coupled to a second even bit line and a second odd bit line, and a controller configured to control the first and the second page buffers so that the second page buffer sets the second even bit line in a floating state such that the voltage of the second even bit line is changed according to a shift in the voltage of the first odd bit line, when a read operation for memory cells coupled to the first odd bit line is performed, and the second page buffer stores data corresponding to the level of threshold voltages of the memory cells by detecting a shift in the voltage of the second even bit line.