Semiconductor Memory Page Buffer Latch Circuit Design
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing program operations due to limitations in controlling bit line voltages during sub-verify and main verify operations, which affect the threshold voltage distribution of memory cells.
Innovation Solution
The semiconductor memory device incorporates a page buffer with first, second, and third latch circuits to manage bit line voltages, applying program-inhibit voltages and enabling voltages to control the threshold voltage distribution by storing and raising voltages accordingly during program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple sub-verify operations with different verify voltages are performed, then threshold voltage distribution characteristics are improved, but device complexity increases due to multiple latch circuits and voltage control mechanisms
Solution Approach 1:
The page buffer is segmented into multiple latch circuits (first latch circuit, second latch circuit, third latch circuit) that separately store data from different verify operations. Each latch circuit corresponds to a specific verify voltage level (main verify voltage, first sub-verify voltage, second sub-verify voltage), enabling independent management of threshold voltage ranges while maintaining overall system functionality.
2Measurement precision
If bit line voltages are differently controlled for memory cells in different threshold voltage ranges, then program operation precision is improved, but control logic complexity increases
Solution Approach 1:
Different bit line voltage control strategies are applied to different memory cell groups based on their threshold voltage characteristics. Memory cells are divided into regions (first region with threshold voltages between second sub-verify and first sub-verify voltages, second region with threshold voltages between first sub-verify and main verify voltages, third region with threshold voltages above main verify voltage), and each region receives customized voltage control through corresponding latch circuits and control logic.
3Productivity
If program-inhibit voltage is applied to bit lines coupled to program-completed memory cells, then program operation efficiency is improved, but additional control circuits are required
Solution Approach 1:
The latch circuits provide feedback about the program completion status of memory cells to the control logic. Based on the stored data from verify operations, the control logic determines which bit lines should receive program-inhibit voltage, enabling efficient program operation by avoiding redundant operations on already-programmed cells while using the feedback information to control the inhibit voltage application.
Data Source
AI summary
Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells, a plurality of page buffers respectively coupled to the plurality of memory cells through bit lines, and a control logic configured to control a program operation of each of the plurality of page buffers. Each of the plurality of page buffers may include a first latch circuit configured to store first data indicating a main verification result obtained using a main verify voltage, a second latch circuit configured to store second data indicating a first sub-verification result obtained using a first sub-verify voltage lower than the main verify voltage, and a third latch circuit configured to store third data indicating a second sub-verification result obtained using a second sub-verify voltage lower than the first sub-verify voltage.