Memory Device Page Buffer Latches for Faster Bit Line Precharging
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Solution Overview
Problem
Existing memory devices require significant time for precharging bit lines during verify operations, which hampers the efficiency of program operations.
Innovation Solution
A memory device with a page buffer system that includes latches to store precharge data, allowing for the setting of precharge voltages based on the program state of memory cells, thereby optimizing the precharge process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If precharge data is set after program voltage application is completed, then the verify operation can be performed accurately, but the time required for bit line precharging increases
Solution Approach 1:
The patent applies preliminary action by setting precharge data in the page buffer during the program voltage application period (operation S803). This allows the precharge operation to be prepared in advance rather than waiting until the program voltage is completely applied, thereby reducing the time required for bit line precharging during the verify operation while ensuring accurate verification can proceed
2Loss of time
If precharge data is set during program voltage application, then the bit line precharging time is reduced, but the program operation complexity increases
Solution Approach 1:
The patent implements self-service by utilizing the existing page buffer structure and its natural operation cycles. The page buffer automatically stores precharge data during program voltage application and autonomously performs the precharge operation during verify, without requiring additional complex control circuits or external intervention. This maintains simplicity while achieving faster precharging
Data Source
AI summary
Provided herein is a memory device related to precharging a bit line and a method of operating the memory device. The memory device including a plurality of memory cells each connected to any one of a plurality of word lines, the any one of the plurality of word lines being a selected word line, and programmed to any one of a plurality of program states, a row decoder configured to apply a program voltage or a verify voltage to the selected word line, and a plurality of page buffers connected to the plurality of memory cells through a plurality of bit lines and configured to store precharge data used to determine a precharge voltage of a target bit line connected to a verify target memory cell among the plurality of bit lines while the program voltage is applied to the selected word line.