Memory Page Buffer Simultaneous Multi-Bit Programming
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Solution Overview
Problem
Higher data densities in nonvolatile memory arrays result in increased delays during program and program verify steps due to multiple program and verify levels per cell, which hinder efficient memory operation.
Innovation Solution
The implementation of a memory device with a plurality of page buffers and control circuitry that sets different target voltages simultaneously for multiple bit lines, allowing for parallel programming and verification of multiple logical values, thereby reducing the duration of program and verify steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits per cell are stored to increase data density, then memory density is improved, but program and program verify step duration increases
Solution Approach 1:
The patent segments the programming operation by dividing the memory array into multiple pages, each handled by a dedicated page buffer circuit. This allows different pages to be programmed simultaneously with different target voltages, effectively parallelizing the programming process across multiple cells while maintaining the multi-bit per cell storage capability for high density.
Solution Approach 2:
The patent introduces a new dimension of parallelism by enabling multiple page buffer circuits to operate simultaneously on different pages. Each page buffer circuit independently programs its assigned page with different target voltages in parallel, transforming a sequential programming process into a parallel one that reduces overall programming time while maintaining high memory density through multi-bit per cell storage.
2Quantity of substance
If multiple program levels and program verify levels are implemented to store more bits per cell, then data density is improved, but the number of programming steps increases
Solution Approach 1:
The patent implements preliminary action by having each page buffer circuit pre-determine and prepare the specific target voltage for its assigned page before the programming operation begins. This preconfiguration allows the programming to proceed in a single parallel step rather than requiring multiple sequential programming steps for different voltage levels, thus reducing the number of programming steps while maintaining multi-bit per cell capability.
Solution Approach 2:
The patent introduces dynamic adaptability by allowing each page buffer circuit to independently select and apply different target voltages based on the specific programming requirements of its assigned page. This dynamic approach enables flexible handling of different programming scenarios (single-level vs. multi-level programming) within the same architecture, reducing the overall complexity of programming steps while maintaining high data density.
3Manufacturing precision
If sequential programming of multiple logical levels is used, then programming accuracy is maintained, but programming time increases
Solution Approach 1:
The patent segments the programming task across multiple independent page buffer circuits, each responsible for a specific page. This segmentation allows simultaneous programming operations on different pages with different target voltages, maintaining programming accuracy through controlled parallel operations while significantly reducing total programming time compared to sequential processing.
Solution Approach 2:
The patent incorporates feedback mechanisms where page buffer circuits monitor and verify the programming results in parallel. This feedback approach ensures programming accuracy by allowing immediate verification of programmed values while the parallel architecture continues to reduce overall programming time through concurrent operations on multiple pages.
Data Source
AI summary
One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.