Non-volatile Memory Page Buffer Sensing Noise Reduction
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Solution Overview
Problem
Multi-bit memory devices face complications such as decreased read margins and increased error rates due to the challenge of effectively sensing and storing more than one bit of data per memory cell, particularly in nonvolatile semiconductor memory devices like flash memory.
Innovation Solution
A nonvolatile memory device with a cell array connected to bit lines in an all bit line structure, a page buffer circuit, and control logic that controls the page buffer circuit to perform coarse and fine sensing operations in different read modes, reducing common source line noise and improving read operation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit memory devices store more than one bit of data per memory cell, then storage capacity is increased, but read margins decrease and error rates increase
Solution Approach 1:
The bit line is divided into multiple independent sensing units, each capable of sensing data from specific memory cells. This segmentation allows parallel sensing of multiple bits while maintaining adequate signal strength for each individual bit, thereby preserving read margins even as storage capacity increases.
Solution Approach 2:
A page buffer circuit is introduced as an intermediary between the memory cell array and the external interface. The page buffer performs sensing operations and data latching, isolating the sensing process from external noise and interference. This intermediary structure improves signal integrity and reduces error rates in multi-bit memory operations.
2Quantity of substance
If multi-bit memory devices store more than one bit of data per memory cell, then storage capacity is increased, but error rates increase
Solution Approach 1:
The page buffer circuit incorporates feedback mechanisms that monitor sensing results and adjust sensing parameters dynamically. This feedback control enables error detection and correction during the sensing process, thereby reducing error rates while maintaining high storage capacity through multi-bit operations.
Solution Approach 2:
The page buffer circuit is designed with adequate signal conditioning and noise filtering capabilities that prepare and protect the sensed signals before they are processed further. This prior cushioning of the signal path prevents noise-induced errors from propagating, thereby reducing error rates in multi-bit memory operations.
3Quantity of substance
If all bit line structure is used to connect cell array to page buffer, then storage capacity and accessibility are improved, but sensing noise increases
Solution Approach 1:
The all bit line structure is segmented into multiple independent sensing units within the page buffer, each handling specific bit lines. This segmentation allows selective sensing and reduces the cumulative noise from all bit lines simultaneously, thereby reducing sensing noise while maintaining the high storage capacity enabled by the all bit line structure.
Solution Approach 2:
Different regions of the page buffer circuit are designed with specialized noise reduction characteristics tailored to their specific sensing functions. This local optimization of noise immunity in different parts of the circuit maintains signal integrity across the all bit line structure, reducing overall sensing noise while preserving storage capacity.
Data Source
AI summary
A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.