Memory Page Buffer Layout for ECC Parity Storage
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Solution Overview
Problem
Semiconductor memory devices face challenges in reducing size due to the need for separate registers to temporarily store parity data for error correction operations, which occupy additional space.
Innovation Solution
The semiconductor memory device incorporates page buffers to temporarily store parity data, allowing for error correction operations without the need for separate registers, thereby reducing device size by integrating this functionality into existing memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate registers are used to temporarily store parity data for error correction operations, then error correction functionality is ensured, but device size increases
Solution Approach 1:
The patent merges the parity data storage function with the existing page buffer structure. Instead of using separate dedicated registers for parity data, the invention utilizes the page buffer's existing memory cells and bit line interface to temporarily store both normal data and parity data. This consolidation eliminates the need for additional parity storage registers, thereby reducing device area while maintaining error correction functionality.
Solution Approach 2:
The page buffer is designed to perform multiple functions: storing normal data during program operations, storing parity data for error correction, and facilitating data transmission between memory blocks and external devices. By making the page buffer universal and multi-functional, the invention eliminates the need for dedicated parity storage registers, thus reducing overall device size while ensuring reliable error correction operations.
2Area of stationary object
If page buffers are used to store parity data instead of separate registers, then device size is reduced, but buffer management complexity increases
Solution Approach 1:
The invention dynamically allocates and manages the page buffer resources based on operational mode. During program operations, the page buffer stores normal data; during error correction operations, it stores parity data. The buffer management logic adaptively switches between these modes and selectively activates appropriate bit line interfaces, thereby handling the increased complexity through dynamic resource allocation rather than static dedicated structures.
Solution Approach 2:
The page buffer structure is designed to self-manage its dual functionality through existing control logic and bit line interfaces. The same bit lines used for normal data access are reused for parity data access during error correction operations. This self-service approach allows the buffer to handle multiple functions without requiring entirely separate management circuits, thus limiting the increase in device complexity.
3Device complexity
If the same bit line interface is used for both normal data and parity data access, then device complexity is reduced, but access speed may be affected
Solution Approach 1:
The invention employs periodic or sequential access patterns for normal data and parity data through the shared bit line interface. During error correction operations, the system periodically switches between accessing normal data and parity data based on operational requirements. This periodic action allows the same interface to serve multiple purposes while maintaining acceptable access speeds through time-division multiplexing rather than requiring parallel dedicated interfaces.
Data Source
AI summary
Provided herein is a semiconductor memory device. The semiconductor memory device may include a plurality of planes including a plurality of memory cells, read/write circuits coupled to the plurality of planes, respectively, and temporarily storing normal data inputted from an external device, random data, and parity data, and an error correction circuit generating the random data by randomizing the normal data, generating parity data for the random data during a program operation, correcting an error of the random data by using the parity data and de-randomizing the random data during a read operation.