Semiconductor Memory Page Buffer Circuit Pre-Verify Skip Logic
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Solution Overview
Problem
Current semiconductor memory devices require extensive program verify operations, which increase overall program operation time and efficiency limitations.
Innovation Solution
A semiconductor memory apparatus and method that includes a page buffer circuit with a sensing latch circuit for data sensing during program verify operations using pre-verify and final verify voltages, a data latch circuit for storing program verify results, and a pass/fail determination circuit to control operations based on these results, allowing for the skipping of subsequent verify operations on memory cells that pass the pre-verify test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive program verify operations are performed to ensure data accuracy, then reliability is improved, but program operation time increases
Solution Approach 1:
The program verify operation is divided into two distinct stages: pre-verify operation using a first verify voltage and final verify operation using a second verify voltage. This segmentation allows the system to perform a quick initial check with lower voltage requirements, then conditionally proceed to the more thorough final verification only when necessary, thereby reducing overall verification time while maintaining data accuracy.
Solution Approach 2:
The pre-verify operation is performed before the final program verify operation to preliminarily assess whether the memory cell has been successfully programmed. By conducting this preliminary check with a first verify voltage, the system can identify clearly failed cells early and skip unnecessary final verification steps for those cells, reducing the total time required for verify operations across the memory array.
2Measurement precision
If multiple verify operations are performed on all memory cells, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The patent applies partial verification by performing the final program verify operation selectively rather than universally. After the pre-verify operation identifies memory cells that fail to store data correctly, the final verify operation is applied only to those specific cells that require it. This partial action approach maintains high verification accuracy for problematic cells while avoiding redundant verification of successfully programmed cells, thereby improving overall program operation efficiency.
3Reliability
If comprehensive pass/fail checks are performed on all memory cells, then reliability is improved, but device complexity increases
Solution Approach 1:
The pass/fail determination process is segmented into two distinct determination stages corresponding to the two verify operations. The first pass/fail determination circuit evaluates results from the pre-verify operation, and only memory cells that fail this initial check proceed to the second pass/fail determination based on the final verify operation. This segmented approach simplifies the control logic compared to a single comprehensive verification system, as each stage has a focused decision-making function.
Data Source
AI summary
A semiconductor memory apparatus includes: a page buffer circuit, a pass/fail determination circuit, and an operation control circuit. The page buffer circuit may include a sensing latch circuit and a data latch circuit. The pass/fail determination circuit determines a pass/fail for a memory cell. The operation control circuit controls a program operation and a program verify operation to be performed on the memory cell.