Semiconductor Memory Page Buffer LSB MSB Read Sequence
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Solution Overview
Problem
In semiconductor memory devices, the high integration and multi-bit storage capabilities lead to a coupling effect where threshold voltages of memory cells can shift during programming, affecting data accuracy and requiring efficient methods to read and program multi-level cells without interference.
Innovation Solution
A method is introduced where a page buffer is coupled to each bit line, allowing for simultaneous reading of least significant bit (LSB) and most significant bit (MSB) data by altering the sequence of page address selection and data read operations, ensuring accurate and sequential data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit cell design is implemented to increase storage capacity, then the quantity of data stored per cell increases, but the threshold voltage stability deteriorates due to coupling effects from neighboring cells
Solution Approach 1:
The patent segments the data storage into separate LSB and MSB pages within the same physical cell structure. By dividing the programming operation into two distinct phases (first programming the LSB page, then programming the MSB page), the method isolates the threshold voltage shifts that occur during programming to specific segments, preventing them from affecting the other segment. This segmentation allows the system to maintain stable threshold voltages while increasing storage capacity to 2 bits per cell.
Solution Approach 2:
The patent applies preliminary action by first programming the LSB page and verifying it before programming the MSB page. This sequential approach with intermediate verification ensures that the threshold voltage shifts caused by the first programming operation are stabilized and recorded before the second programming operation begins. The flag cell mechanism also serves as a preliminary indicator to track the programming state, preventing interference between the two programming phases.
2Measurement precision
If sequential reading of data is performed, then data can be read accurately, but the read time increases
Solution Approach 1:
The patent merges the reading of LSB and MSB data into a single simultaneous read operation. By designing the page buffer to hold both LSB and MSB data and enabling parallel read access to both pages, the method combines what would traditionally be two separate read operations into one. This merging maintains reading accuracy for both data segments while significantly reducing the total read time, as both bits are read concurrently rather than sequentially.
Solution Approach 2:
The patent introduces a dimensional change in the read operation by enabling simultaneous access to both LSB and MSB pages through the page buffer. Instead of reading data in a single-dimensional sequential manner, the system creates a two-dimensional read structure where both pages can be accessed at the same time. This dimensional expansion allows parallel data retrieval, reducing read time without compromising accuracy.
3Productivity
If page buffer is coupled to each bit line for simultaneous LSB and MSB reading, then read efficiency increases, but device complexity increases
Solution Approach 1:
The patent makes the page buffer multi-functional by designing it to handle both LSB and MSB data storage and retrieval operations. Instead of requiring separate dedicated buffers for each data type, the single page buffer structure performs multiple functions: storing LSB data, storing MSB data, and facilitating simultaneous read operations for both. This universality reduces the overall number of components needed while maintaining high read efficiency for both data segments.
Solution Approach 2:
The patent implements a nested structure where the LSB and MSB pages are organized within the same physical memory structure and page buffer system. The flag cell mechanism is nested within the memory array to track programming states, while the page buffer嵌套holds both data types in an integrated manner. This nesting allows the system to achieve simultaneous reading capability without proportionally increasing the number of separate buffer structures, thereby limiting the increase in device complexity.
Data Source
AI summary
A semiconductor memory device is operated by reading data stored in LSB and MSB pages of a first word line in response to a read command and storing the read data in first and second latches of a page buffer, outputting the data stored in the first latch externally and transferring the data, stored in the second latch, to a third latch of the page buffer, resetting the first and second latches, reading data stored in LSB and MSB pages of a second word line, and storing the read data in the first and second latches, and sequentially outputting the data stored in the first latch and the data stored in the third latch, resetting the third latch, and then transferring the data stored in the second latch to the third latch.