Non-volatile Memory Page Buffer Segmentation for Bit Line Coupling
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Solution Overview
Problem
Conventional non-volatile memory devices face malfunctions due to coupling between bit lines during read and verify operations, especially with the multi-level cell technique, which reduces the distance between threshold voltages and increases the likelihood of errors.
Innovation Solution
A non-volatile memory device with a page buffer that includes precharge units for both even and odd bit lines, allowing simultaneous precharging and evaluation of bit lines to prevent floating and coupling issues, using registers and transistors to manage sense nodes and bit lines effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one sense node is used for both even and odd bit lines, then device complexity is reduced, but coupling between bit lines occurs causing read errors
Solution Approach 1:
The patent divides the bit line system into separate even bit lines and odd bit lines, each with dedicated sense nodes and precharge units. This segmentation prevents coupling between adjacent bit lines while maintaining manageable device complexity through systematic organization of the divided components.
2Use of energy by moving object
If bit lines are kept floating during sensing, then power consumption is reduced, but coupling capacitance causes incorrect data output
Solution Approach 1:
The patent applies preliminary precharging action to sense nodes before read or verify operations. By precharging sense nodes to a known state and maintaining controlled voltage levels during sensing, the system eliminates coupling capacitance interference without requiring bit lines to remain completely floating, thus ensuring accurate data output.
3Quantity of substance
If multi-level cell technique is applied to store multiple bits per cell, then storage density is increased, but threshold voltage distance between states is reduced increasing malfunction risk
Solution Approach 1:
The patent segments bit lines into even and odd groups with dedicated precharge units and sense nodes for each. This segmentation isolates the sensing process for multi-level cells, preventing coupling interference that could cause malfunctions when threshold voltage distances between states are reduced, thereby maintaining program verify accuracy despite increased storage density.
4Device complexity
If sequential programming of even and odd bit lines is used, then device complexity is reduced, but productivity is decreased due to one-at-a-time processing
Solution Approach 1:
The patent segments the bit line interface into independent even and odd channels, each with dedicated precharge units and sense nodes. This segmentation enables parallel programming and verification operations on even and odd bit lines simultaneously, significantly improving productivity while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The patent merges the functionality of multiple sense nodes into a unified page buffer structure that can simultaneously handle even and odd bit line operations. By combining the control logic and buffer resources, the system achieves parallel processing capability without proportionally increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable data read and program verify operations by preventing malfunctions caused by bit line coupling, allowing for increased data read and verify rates compared to conventional methods.
Implementation Method 1
the bit line is generally kept floating. In the case where a word line including a programmed cell and an erased cell in two neighboring bit lines is selected, the two bit lines influence each other by coupling capacitance
Data Source
AI summary
A non-volatile memory device includes an even bit line and an odd bit line, a first register, a second register, a first precharge unit, a second precharge unit and a bit line select unit. The even bit line and the odd bit line are connected to a memory cell array. The first register is connected to the even bit line and configured to store specific data. The second register is connected to the odd bit line and configured to store specific data. The first precharge unit precharges an even sense node, formed at a node of the even bit line and the first register, with a high level or supplies supplementary current to the even sense node. The second precharge unit precharges an odd sense node, formed at a node of the odd bit line and the second register, with a high level or supplies supplementary current to the odd sense node. The bit line select unit connects the even bit line and the even sense node and connects the odd bit line and the odd sense node.