Semiconductor Memory Page Buffer for Bit-Line Stability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor memory devices face challenges in maintaining a sufficient sensing margin during read operations, particularly due to variations in bit line potentials and current levels, which affect data sensing accuracy.

Innovation Solution

The implementation of a page buffer with a first current supply circuit that connects or blocks a power voltage node to a common sensing node based on bit line potential, a second current supply circuit that controls the sensing node's potential level based on current amount, and a latch unit that latches data based on the sensing node's potential, along with a bit line potential adjusting circuit for initial setting and a read/write circuit for data sensing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional read operations are performed without dynamic current supply control, then the circuit operation is simple, but the sensing margin is insufficient due to bit line potential variations

Engineering Contradiction:
Improvesensing marginVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic current supply control where the current supply circuit adjusts its operation based on the potential level of the bit line. During read operations, the circuit transitions from a static to a dynamic state, activating additional current paths when bit line potential drops below a threshold, thereby maintaining sufficient sensing margin adaptively without requiring complex additional circuitry.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The page buffer circuit monitors its own bit line potential and automatically activates the first current supply path when needed. The circuit uses its internal resources (the first and second current supply circuits) to self-correct potential drops, eliminating the need for external intervention or complex control mechanisms while maintaining reliable sensing.

Inventive Principle:
Principle #25Self-service

2Measurement precision

If the sensing node potential is not actively controlled, then the circuit operation is simpler, but the data sensing accuracy deteriorates due to current amount variations

Engineering Contradiction:
Improvedata sensing accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the potential level of the bit line is continuously monitored, and this information feeds back to control the activation of the first current supply circuit. The sensing node potential is actively controlled based on this feedback, ensuring that data sensing accuracy is maintained despite variations in current amount, while avoiding unnecessarily complex control logic.

Inventive Principle:
Principle #23Feedback

3Reliability

If bit line potential is not adjusted during read operations, then the operation speed is faster, but the data read reliability decreases due to insufficient sensing margin

Engineering Contradiction:
Improvedata read reliabilityVSAvoidread operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent prepares the bit line potential adjusting circuit in advance during the read operation setup phase. The circuit is configured to automatically activate the first current supply path when bit line potential drops, ensuring that the sensing margin is maintained without requiring additional time for potential adjustment during the actual sensing phase. This preliminary preparation enables both high reliability and fast operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12455690B2Page buffer, semiconductor memory having the same, and operating method thereof
Publication Date: 2025.10.28 SK HYNIX INC
  • US12455690B2 patent drawing
  • US12455690B2 patent drawing
  • US12455690B2 patent drawing

AI summary

A page buffer, a semiconductor memory having the same, and an operating method thereof are provided. The page buffer includes a first current supply circuit connected to a bit line, the first current supply circuit connecting or blocking a power voltage node to or from a common sensing node based on a potential level of the bit line; a second current supply circuit for controlling a potential level of a sensing node based on a current amount of the common sensing node; and a latch unit for latching data based on a potential of the sensing node.