Semiconductor Memory Page Buffer Separation
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Solution Overview
Problem
The miniaturization of memory cells in non-volatile semiconductor memory devices leads to the proximity effect, causing fluctuations in threshold values, which complicates data storage and requires additional correction techniques to narrow the threshold distribution width, while existing methods like the LM and additional writing methods slow down the write operation due to the need to read page flag data.
Innovation Solution
A semiconductor integrated circuit device with a memory cell array and a page buffer that includes user and page flag regions, where page flag data is recorded in two levels and user data in multiple levels, allowing for efficient data writing and reading by utilizing a page buffer with separate sections for user and page flag data, reducing the need for repeated read operations and enhancing write speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If page flag data is read to correct threshold value fluctuations, then manufacturing precision is improved, but productivity deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines before reading page flag data. This preparatory step reduces the time required for subsequent read operations, allowing threshold value correction without significantly impacting write operation speed. The bit line pre-charging is performed in advance of the actual data read, eliminating delays that would otherwise occur during the correction process.
2Productivity
If miniaturization of memory cells is advanced to increase storage capacity, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent implements feedback by reading page flag data that indicates the current state of memory cells and using this information to adjust subsequent write operations. This feedback mechanism detects threshold value fluctuations caused by the proximity effect in miniaturized cells and compensates for them, maintaining manufacturing precision despite increased storage capacity through cell miniaturization.
Solution Approach 2:
The patent replaces physical spacing mechanisms with an electrical/algorithmic correction system. Instead of relying on physical separation between miniaturized cells to prevent interference, the system uses bit line pre-charging and page flag data reading to detect and correct threshold fluctuations, substituting mechanical design constraints with electronic compensation techniques.
Data Source
AI summary
A semiconductor integrated circuit device has a memory cell array including a plurality of pages and a page buffer. Each of the plurality of pages includes a user region and a page flag region in which page flag data indicative of a current state of a corresponding page is written. The page buffer includes a user page buffer section which temporarily holds the user data and a page flag page buffer section which temporarily holds the page flag data. The page flag data is recorded in the form of two levels in the non-volatile semiconductor memory cell arranged in the page flag region. The user data is recorded in the form of multilevel in the non-volatile semiconductor memory cell arranged in the user region.