Semiconductor Memory Page Buffer Blocks With Shared Decoders
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing size while maintaining effective page buffer circuit functionality, particularly in the arrangement and electrical connections of page buffer blocks.
Innovation Solution
The semiconductor device incorporates unit page buffer blocks with four page buffer pairs arranged in a column direction, each comprising a common column decoder block and both upper and lower page buffer stages, which are electrically connected. These stages include selection, latch, and cache blocks arranged in specific configurations to optimize electrical connections and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If page buffer blocks are arranged with multiple page buffer pairs, then data processing capability is improved, but device area increases
Solution Approach 1:
Multiple page buffer pairs (first and second page buffer pairs) share common column decoder blocks and bit line sets, merging functional resources to reduce overall device area while maintaining enhanced data processing capability through parallel buffer operations
Solution Approach 2:
The common column decoder blocks serve multiple page buffer pairs simultaneously, and bit line sets are shared across different buffer pairs, enabling single resources to perform multiple functions and support increased productivity without proportional area increase
2Area of stationary object
If page buffer pairs are arranged in column direction with shared resources, then device area is reduced, but electrical connection complexity increases
Solution Approach 1:
The page buffer circuit is divided into distinct upper and lower page buffer stages, each with dedicated selection, latch, and cache blocks, segmenting the electrical connections into manageable sections that reduce overall complexity despite multiple shared resources
Solution Approach 2:
Page buffer pairs are arranged in a two-dimensional layout with upper and lower stages connected to common column decoders, utilizing spatial dimensionality to organize electrical connections systematically rather than linearly, reducing connection complexity
Data Source
AI summary
A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.