Memory Page Buffer with Temporary Storage Node for Program Time Reduction
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing the time required for program operations, particularly due to the need to maintain target state information in sensing latches during bit line precharge operations.
Innovation Solution
The proposed solution involves a memory device with a page buffer that includes data latches, a sensing latch, a temporary storage node, and a control logic circuit. This configuration allows for the transfer of target state information from the sensing latch to the temporary storage node, enabling selective precharging of bit lines based on the temporary storage node's level, and concurrently performing dump operations for next target state information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If target state information is maintained in sensing latch during bit line precharge operation, then verify operation can be performed correctly, but program time increases due to sequential operation requirement
Solution Approach 1:
A temporary storage node is introduced as an intermediary between the sensing latch and the bit line precharge circuit. The target state information is first transferred to this temporary storage node, which then controls the selective precharging of bit lines. This intermediary structure allows the sensing latch to be freed for the next dump operation while the precharge operation proceeds independently, enabling overlapping of operations and reducing total program time without compromising verify operation correctness.
Solution Approach 2:
The target state information is transferred to the temporary storage node in advance, before the bit line precharge operation begins. This preliminary action prepares the control signal for precharging while the sensing latch is still holding the information, allowing the sensing latch to be reused for the next dump operation during the precharge process, thus enabling parallel execution and reducing overall program time.
2Reliability
If dump operation for next target state information is performed after bit line precharge operation completes, then data integrity is maintained, but verify step time increases
Solution Approach 1:
The dump operation for next target state information is performed continuously during the bit line precharge operation rather than waiting for its completion. The temporary storage node provides the control signals for selective precharging while the sensing latch simultaneously performs the dump operation, ensuring both operations proceed without interruption and overlap in time, thereby maintaining data integrity while reducing verify step duration.
Solution Approach 2:
The system dynamically manages the timing and control signals for both the precharge operation and dump operation. The temporary storage node dynamically provides control signals for precharging based on the target state information, while the sensing latch dynamically performs dump operations for next target state information, allowing flexible overlapping of operations and optimization of verify step time without compromising data integrity.
Data Source
AI summary
Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.