Semiconductor Memory Page Buffer Bit Line Select Transistor Path Length Equalization
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Solution Overview
Problem
Semiconductor memory devices with stacked memory chips face differences in operation speed due to varying path lengths of bit line select transistors, leading to inefficiencies in data charging and discharging during program, read, and erase operations.
Innovation Solution
Incorporating bit line select transistors in each memory chip and through-chip interconnectors to equalize the path lengths and improve data transfer efficiency, while using high-voltage elements for erase operations and low-voltage elements for latch operations to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit line select transistors are placed only in the circuit chip, then device complexity is reduced, but operation speed differences occur between stacked memory chips due to varying path lengths
Solution Approach 1:
The bit line select transistor function is segmented and distributed: one transistor is placed in the circuit chip while another is placed in each memory chip. This segmentation equalizes the bit line path lengths between different stacked memory chips, ensuring uniform operation speeds while maintaining manageable device complexity through functional distribution.
2Speed
If through-chip interconnectors are increased to equalize path lengths, then operation speed uniformity improves, but manufacturing cost increases
Solution Approach 1:
Instead of uniformly increasing interconnectors throughout the stacked structure, the solution applies local quality by placing bit line select transistors at specific locations (in the circuit chip and in each memory chip). This targeted approach equalizes path lengths and improves operation speed uniformity without requiring excessive interconnectors, thereby controlling manufacturing costs.
3Productivity
If high-voltage elements are used throughout the page buffer circuit, then erase operation performance improves, but power consumption increases
Solution Approach 1:
The page buffer circuit uses local quality by employing high-voltage elements only where needed for erase operations (in the memory chips) and low-voltage elements for latch operations (in the circuit chip). This differentiated voltage approach maintains excellent erase operation performance while significantly reducing overall power consumption by applying appropriate voltage levels to specific functional regions.
Data Source
AI summary
A semiconductor memory device includes a latch defined on a circuit chip; and a bit line select transistor defined in a first memory chip stacked in the circuit chip and a second memory chip stacked on the first memory chip. The bit line select transistors exchange data with the latch.