Memory Page Buffer Temperature Compensation via Trip Control Transistor
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Solution Overview
Problem
Memory devices face performance degradation due to decreased cell current at lower temperatures, limiting effective compensation methods for voltage levels in bit lines, which can lead to sensing failures.
Innovation Solution
A page buffer circuit with a trip control transistor and a control circuit that adjusts voltage signals, including a trip control voltage, to increase the sensing trip level as temperature decreases, enhancing data read performance by managing shut-off, bit line connection, and bit line clamping control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage level of bit lines is increased to compensate for reduced cell current at lower temperatures, then the cell current compensation is improved, but the voltage level restriction limits the compensation effectiveness
Solution Approach 1:
The patent changes the parameter of trip control voltage to dynamically adjust the sensing trip level of the page buffer. By varying the trip control voltage based on temperature conditions, the sensing threshold adapts to compensate for reduced cell current at lower temperatures without being constrained by fixed bit line voltage levels.
Solution Approach 2:
The patent introduces dynamic adjustment of the sensing trip level through the trip control transistor, which modulates the switching threshold based on temperature-dependent voltage control. This dynamic mechanism allows the system to adapt to changing thermal conditions rather than relying on static voltage compensation.
2Measurement precision
If the trip control voltage level is increased to raise the sensing trip level at lower temperatures, then the sensing accuracy is improved, but the complexity of voltage control increases
Solution Approach 1:
The trip control transistor serves as an intermediary element between the control circuit and the sensing node. It translates the trip control voltage into an adjusted sensing trip level, providing a simple yet effective mechanism for precision control without requiring complex circuitry directly at the sensing node.
3Reliability
If multiple control signals are adjusted to compensate for temperature effects, then the temperature compensation effectiveness is improved, but the control circuit complexity increases
Solution Approach 1:
The control circuit is designed to manage multiple control signals (shut-off, bit line connection, and bit line clamping) through a unified temperature compensation mechanism. By coordinating these signals under a single control framework that responds to temperature conditions, the system achieves comprehensive compensation without proportionally increasing control complexity.
Data Source
AI summary
A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.