Nonvolatile Memory Page Buffer Circuit Vertical Interconnect
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Solution Overview
Problem
As semiconductor manufacturing advances, higher integration and reduced scale of nonvolatile memory and storage devices lead to new issues that can damage stored data and degrade reliability, such as coupling between bit lines and lines in memory cell arrays, affecting the performance and reliability of these devices.
Innovation Solution
The solution involves a page buffer circuit with bit line selection transistors and latches connected through lines on different planes, reducing coupling between bit lines and lines by using floating lines, thereby enhancing the reliability of nonvolatile memory devices and storage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher integration and reduced scale are implemented, then production costs are reduced and capacity increases, but reliability deteriorates and data damage risks increase
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture where bit lines and lines are positioned on different planes (first plane and second plane) above the substrate. This vertical separation in the third dimension reduces parasitic coupling and interference while maintaining high integration density, thereby improving reliability without sacrificing productivity.
Solution Approach 2:
The patent divides the page buffer circuit into distinct functional components (bit line selection transistors, latches, and bit lines) that are spatially separated and independently positioned on different planes. This segmentation allows each component to be optimized independently and reduces unwanted interactions, enhancing overall device reliability in high-density configurations.
2Device complexity
If bit lines and lines are placed on the same plane, then device complexity is reduced, but coupling between bit lines and lines increases causing malfunction
Solution Approach 1:
The patent resolves the contradiction by moving the system from a two-dimensional plane to a three-dimensional space. Bit lines are positioned on a first plane while lines are positioned on a second plane at a different height above the substrate. This vertical separation eliminates parasitic coupling between these conductors while maintaining a relatively simple circuit architecture, as the additional dimensional complexity is minimal compared to the benefit of eliminating harmful electromagnetic interference.
Data Source
AI summary
The inventive concepts relate to nonvolatile memory devices. The nonvolatile memory devices may include a memory cell array, and a page buffer circuit connected to the memory cell array through bit lines. The page buffer circuit may comprise a substrate, bit line selection transistors on the substrate and connected to respective ones of the bit lines, and latches on the substrate connected to the bit line selection transistors through lines. The lines may be on a first plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through first contacts. The bit lines may be on a second plane above and parallel to a top surface of the substrate, and may be connected to respective ones of the bit line selection transistors through second contacts.