Memory Page Buffer Voltage Stabilization via Unused Node Capacitance
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Solution Overview
Problem
Semiconductor memory devices face challenges in stabilizing internal voltages during high-speed operations due to power noise, which existing methods often address by using additional capacitors that increase costs and area.
Innovation Solution
A memory device and method that stabilize internal voltages without additional capacitors by electrically connecting unused electrical nodes to the internal voltage circuit during latch set operations, utilizing these nodes as capacitors to reduce power noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If additional capacitors are used to stabilize internal voltage during high-speed operations, then power noise is reduced, but device area and cost increase
Solution Approach 1:
The patent makes unused electrical nodes (originally idle resources) serve a dual function: their original function plus serving as capacitors for voltage stabilization. By connecting these floating nodes to the internal voltage circuit during latch set operations, they provide capacitance to reduce power noise without requiring dedicated capacitor components, thus achieving multi-functionality and reducing device area.
Solution Approach 2:
The patent recovers and utilizes electrical nodes that would otherwise be discarded or left unused during certain operations. Specifically, floating nodes from unused page buffers are recovered and temporarily connected to the internal voltage circuit to provide stabilizing capacitance during latch set operations, transforming wasted resources into useful functional elements.
2Object-affected harmful factors
If additional capacitors are used to stabilize internal voltage during high-speed operations, then power noise is reduced, but manufacturing cost increases
Solution Approach 1:
The patent makes unused electrical nodes (originally idle resources) serve a dual function: their original function plus serving as capacitors for voltage stabilization. By connecting these floating nodes to the internal voltage circuit during latch set operations, they provide capacitance to reduce power noise without requiring dedicated capacitor components, thus achieving multi-functionality and reducing device area.
Solution Approach 2:
The patent recovers and utilizes electrical nodes that would otherwise be discarded or left unused during certain operations. Specifically, floating nodes from unused page buffers are recovered and temporarily connected to the internal voltage circuit to provide stabilizing capacitance during latch set operations, transforming wasted resources into useful functional elements.
3Speed
If high-speed operations are performed in the memory device, then operating speed increases, but power noise is generated
Solution Approach 1:
The patent applies preliminary anti-action by proactively connecting floating electrical nodes to the internal voltage circuit before the actual high-speed latch set operation begins. This pre-connection ensures that the capacitance is already in place to counteract the power noise that will be generated during the high-speed operation, rather than attempting to mitigate noise after it occurs.
Solution Approach 2:
The patent implements dynamic connection of electrical nodes to the internal voltage circuit based on operational needs. The connection is temporarily established during latch set operations and disconnected when not needed, allowing the system to adapt its noise mitigation capabilities dynamically according to the operational state, thereby reducing power noise during high-speed operations while maintaining flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively stabilizes internal voltages during high-speed operations, reducing power noise without the need for additional capacitors, thereby minimizing costs and area requirements.
Implementation Method 1
generating by an internal voltage circuit at least one internal voltage among internal voltages used for an operation of the page buffer circuit, the internal voltage circuit providing the at least one internal voltage to the page buffer circuit
Implementation Method 2
providing to the page buffer circuit a control signal for forming an electrical connection between the internal voltage circuit and a first electrical node of a first page buffer unused for buffering in the page buffer circuit
Data Source
AI summary
A method controls a memory device that includes a page buffer circuit comprising a plurality of page buffers each comprising at least one latch. The method includes generating by an internal voltage circuit at least one internal voltage among internal voltages used for an operation of the page buffer circuit, the internal voltage circuit providing the at least one internal voltage to the page buffer circuit; and providing to the page buffer circuit a control signal for forming an electrical connection between the internal voltage circuit and a first electrical node of a first page buffer unused for buffering in the page buffer circuit during a set operation for a first latch of a second page buffer.