Semiconductor Memory Page Buffer Wiring Offset
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Solution Overview
Problem
The challenge in semiconductor memory devices is the coupling failure between page buffers and contacts, which occurs due to the tight overlap margin between active regions and contacts, leading to open failures or high contact resistance, especially as the pitch of bit lines decreases, making it difficult to maintain performance without using expensive high-performance equipment.
Innovation Solution
The semiconductor memory device design includes wiring lines with bent configurations where contact portions are offset toward the center lines of active regions, featuring straight and tilted portions with specific spacing and angles to reduce the likelihood of coupling failures, thereby maintaining performance without the need for expensive equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of bit lines is decreased to increase memory density, then memory capacity is improved, but coupling failure between page buffers and contacts increases
Solution Approach 1:
The wiring line configuration transitions from a simple linear path to a multi-dimensional bent path with tilted portions. The wiring lines include first tilted portions and second tilted portions that angle toward the center line of active regions, creating a three-dimensional routing solution that increases the overlap margin between wiring lines and contacts without increasing the planar pitch of bit lines.
Solution Approach 2:
The wiring lines have non-uniform spacing characteristics - the spacing between adjacent wiring lines varies along their length, being tighter in some regions and wider in others. Specifically, the bent configuration creates local regions with increased overlap margin where contacts are formed, while maintaining tighter spacing in other regions to preserve memory density.
2Reliability
If high-performance equipment is used to prevent coupling failure, then coupling reliability is improved, but manufacturing cost increases
Solution Approach 1:
The design changes the geometric parameters of wiring lines - specifically the angle and extent of tilted portions - to optimize the overlap margin. By adjusting these parameters, the patent achieves reliable coupling without requiring expensive high-performance manufacturing equipment, as the solution relies on geometric optimization rather than advanced process capabilities.
3Quantity of substance
If wiring lines are positioned closer to active region edges to increase density, then memory density is improved, but overlap margin between wiring lines and contacts decreases
Solution Approach 1:
The wiring lines incorporate curved bent configurations with tilted portions instead of straight linear paths. These curved segments are positioned to offset toward the center line of active regions, creating a geometric arrangement that maintains adequate overlap margin while allowing wiring lines to be positioned closer to active region edges for increased density.
Data Source
AI summary
A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.