Sectioned Memory Page Copy via BLSABF Signal Propagation
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Solution Overview
Problem
Conventional semiconductor memory blocks face a tradeoff between prefetch number, power consumption, normalized access energy efficiency, and memory block area, with existing cell array architectures reaching limitations in prefetch number without significant area increase.
Innovation Solution
A novel memory module architecture that divides the memory cell array into sections, using bit-line sense-amplifiers/buffers (BLSABFs) to propagate data voltage signals across adjacent sections through a series of BLSABFs, coupled with page buffers to manage data access efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional cell array architecture is used to increase prefetch number, then data access bandwidth is improved, but memory block area must be significantly increased
Solution Approach 1:
The memory block is divided into multiple memory sections, each with its own sense amplifier. Data is segmented and transmitted through multiple parallel paths simultaneously, enabling increased prefetch number without proportionally increasing the total memory block area. The segmentation allows efficient utilization of existing space through parallel data transmission channels.
2Productivity
If conventional cell array architecture increases prefetch number, then data access bandwidth is improved, but power consumption increases
Solution Approach 1:
Sense amplifiers perform preliminary data sensing and voltage signal generation in advance within each memory section. This preliminary action allows data to be prepared and staged for transmission, reducing the energy required during the actual data transfer phase. The preliminary sensing enables more efficient power utilization when increasing prefetch capabilities.
3Productivity
If conventional cell array architecture increases prefetch number, then data access bandwidth is improved, but normalized access energy efficiency deteriorates
Solution Approach 1:
Multiple memory sections are merged into a unified data transmission system where sense amplifiers from different sections work in parallel. The merging of these sections creates efficient data pathways that reduce per-bit energy consumption. By combining resources across sections and utilizing shared transmission channels, the system achieves better normalized energy efficiency despite increased prefetch operations.
Data Source
AI summary
An apparatus for page-copy data accessing is provided, which includes a memory cell array, bit-line sense-amplifier/buffers (BLSABFs), page buffers and a logic operation processing circuit. Data voltage signals on bit-lines in a memory section are transferred to the bit-lines in an adjacent memory section adjacent to the memory section by BLSABFs and the voltage data signals are sequentially propagated across subsequent memory sections through BLSABFs between the subsequent memory sections. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising target location to write voltages to the memory cells at the target location. The page buffers are configured to receive data voltage signals from the coupled BLSABFs to a data interface.