Internal Memory Page Copying via Dedicated Sense Amplifiers
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Solution Overview
Problem
Bulk data operations in computer systems, such as page copying, resetting, and inverting memory contents, lead to high latency and energy inefficiency due to numerous data transfers over memory channels, degrading system performance and energy efficiency.
Innovation Solution
Implementing a page copy function within the memory chip using internal mechanisms and circuits, allowing for data operations like copying, resetting, and inverting to be performed with minimal external data transactions, utilizing additional pins or command multiplexing to reduce data transfers and leverage internal IO bus architecture for energy-efficient operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred over memory channel to perform bulk data operations, then data operations can be performed, but latency increases and energy efficiency degrades
Solution Approach 1:
The patent extracts the data copying function from the memory controller and relocates it to the memory chip itself. The memory chip now includes internal circuitry to copy data between banks internally, eliminating the need to transfer data over the memory channel for copying operations. This extraction of the copying function from the external controller to the internal chip architecture directly reduces latency and improves productivity.
Solution Approach 2:
The patent introduces an intermediary mechanism within the memory chip - a data buffer and internal data bus system that enables direct data transfer between banks without external intervention. This intermediary internal data path acts as a mediator that bypasses the external memory channel, reducing both latency and energy consumption for data copying operations.
2Productivity
If data is transferred over memory channel to perform bulk data operations, then data operations can be performed, but energy consumption increases
Solution Approach 1:
The patent extracts the energy-intensive data transfer operation from the memory channel and relocates it to internal chip circuits. By moving the copying function inside the memory chip, the system eliminates the need to activate high-power memory channel interfaces for copying operations, significantly reducing energy consumption while maintaining data operation capability.
Solution Approach 2:
The memory chip performs data copying operations on its own using internal resources without requiring external memory channel access. The chip serves itself by implementing internal copying logic and buffers, eliminating the need for energy-consuming external data transfers and making the system more energy-efficient.
3Ease of operation
If presetting or resetting memory contents by writing zero is performed, then memory can be cleared, but large number of data transfers over memory channel are required
Solution Approach 1:
The patent extracts the memory clearing function from external write operations and implements it as an internal chip function. The memory chip includes dedicated circuitry to clear memory contents internally without requiring data transfers over the memory channel, making the clearing operation faster and more efficient.
Solution Approach 2:
Instead of writing zero data to clear memory (which requires data transfers), the patent uses a copying approach where the clear operation is performed internally by the chip's control logic. The chip copies the clear state internally without external data movement, reducing both time and energy requirements for memory resetting.
4Ease of operation
If AVX instructions are used to clear memory pages, then clearing capability is provided, but time and power consumption increase due to looping
Solution Approach 1:
The patent extracts the memory clearing function from software-based AVX instructions and implements it as a hardware function within the memory chip. This extraction eliminates the need for software loops and repeated instructions, providing a single-cycle hardware operation that is both faster and more energy-efficient.
Solution Approach 2:
The patent replaces the software-based mechanical looping mechanism (AVX instructions executed in loops) with a hardware-based electrical circuit implementation. The internal memory clearing circuit performs the operation in a single hardware cycle, substituting the time-consuming software loop with an instantaneous electrical operation.
5Ease of operation
If data is transferred and inverted over memory channel, then data inversion can be performed, but time and power are consumed
Solution Approach 1:
The patent extracts the data inversion function from external memory channel operations and implements it as an internal chip function. The memory chip includes logic to invert data bits internally without requiring data to be transferred over the memory channel, significantly reducing energy consumption while maintaining inversion capability.
Data Source
AI summary
An apparatus comprises: a source array of memory cells with associated source sense amplifiers; a destination array of memory cells with associated destination sense amplifiers; and logic to activate a source word-line (WL) to select a row of memory cells within the source array such that data in the selected row of memory cells is latched by the associated source sense amplifiers, wherein the logic to activate a destination WL to select a row of memory cells within the destination array such that data in the selected row of memory cells is latched by the associated destination sense amplifiers, and wherein the source and destination arrays of memory cells are within a same bank of a memory.