Memory Page Scheduling With Delta Prediction and DNN Preloading
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Solution Overview
Problem
Existing memory access prediction methods, particularly those using deep neural networks (DNNs), face challenges in accurately predicting memory access counts and addresses due to high resource requirements and cumulative errors, making real-time implementation difficult and inefficient.
Innovation Solution
The use of next-delta and far-delta predictions in conjunction with a DNN classifier to convert memory access sequences into delta values, which are then classified and used to preload memory addresses into faster memory systems, reducing latency and energy consumption by leveraging a DNN's predictive capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If deep neural networks are used to predict memory access counts and addresses, then prediction accuracy is improved, but resource requirements and cumulative errors increase making real-time implementation difficult
Solution Approach 1:
The patent segments the memory address prediction problem into two independent parts: next-delta prediction (short-term) and far-delta prediction (long-term). Each segment is handled by a separate DNN classifier with specialized architecture, avoiding the need for a single complex model that would require excessive resources while maintaining high prediction accuracy for both short-term and long-term memory accesses.
Solution Approach 2:
The patent transforms the traditional approach of predicting absolute memory addresses into predicting delta values (differences between consecutive addresses). This dimensional transformation allows the DNN to work with smaller, more manageable value ranges, reducing computational complexity and resource requirements while preserving prediction accuracy.
2Use of energy by moving object
If traditional prediction methods are used, then resource consumption is lower, but cumulative errors increase and latency is higher
Solution Approach 1:
The patent implements preliminary action by preloading memory pages into faster memory (e.g., L2 cache) before they are actually needed by the processor. The DNN-based page scheduler predicts future memory access patterns and proactively loads anticipated pages, eliminating wait time and reducing latency without requiring excessive energy consumption during actual memory operations.
Solution Approach 2:
The patent introduces an intermediary DNN-based page scheduler that acts as a mediator between the processor and memory system. This intermediary component analyzes access patterns, makes intelligent prediction decisions, and manages memory loading operations, thereby reducing overall system latency and energy consumption by optimizing the timing and location of memory operations.
Data Source
AI summary
Disclosed in some examples are improved address prediction and memory preloading that leverages next-delta prediction and/or far-delta prediction for scheduling using a DNN. Previous memory access sequence data that identify one or more memory addresses previously accessed by one or more processors of a system may be processed and then converted into a sequence of delta values. The sequence of delta values are then mapped to one or more classes that are then input to a DNN. The DNN then outputs a predicted future class identifier sequence that represents addresses that the DNN predicts will be accessed by the processor in the future. The predicted future class identifier sequence is then converted back to a predicted delta value sequence and back into a set of one or more predicted addresses.