Compressed Memory Page Layout With Distributed ECC Parity
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Solution Overview
Problem
Existing memory devices face inefficiencies in storing compressed data, as data compression can lead to data loss and reduced storage reliability, particularly when high importance data is compressed, necessitating improved error correction mechanisms.
Innovation Solution
A memory system comprising a data compressor and an error correction block generator that divides compressed data into normal and invalid data with parity, ensuring each error correction block includes normal data, invalid data, and parity, with the invalid data having the same value, distributed across physical pages to enhance error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is compressed to increase storage efficiency, then storage capacity is improved, but data reliability deteriorates due to potential data loss
Solution Approach 1:
The patent divides compressed data into multiple error correction blocks, where each block contains a portion of the compressed data along with dedicated parity information. This segmentation allows independent error correction for each block, maintaining data reliability while preserving storage efficiency gains from compression.
Solution Approach 2:
The patent pre-allocates parity information within each error correction block before data storage. This beforehand cushioning ensures that error correction capability is built into the storage structure in advance, protecting against data loss from compression while maintaining high storage efficiency.
2Reliability
If error correction capability is increased to maintain data reliability, then data protection is improved, but storage efficiency deteriorates due to increased overhead
Solution Approach 1:
The patent applies error correction locally within each error correction block rather than globally across all compressed data. Each block contains its own parity information, allowing targeted error correction that minimizes overhead while maintaining reliability. This local approach prevents the need for excessive global parity data.
Solution Approach 2:
By segmenting compressed data into multiple error correction blocks with distributed parity information, the patent achieves effective error correction without requiring a single large parity section that would reduce storage efficiency. The segmented approach optimizes the balance between protection and capacity.
3Device complexity
If compressed data is stored in fixed-size blocks, then storage organization is simplified, but error correction efficiency deteriorates due to uneven data distribution
Solution Approach 1:
The patent allows the data portion within each error correction block to vary in size while maintaining a fixed total block size. This parameter change enables flexible data distribution across blocks, improving error correction efficiency by ensuring each block has adequate parity coverage without requiring complex variable-size block structures.
Data Source
AI summary
A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit, and an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data, wherein each of the error correction blocks comprises the normal data, invalid data having a size corresponding to the size of the normal data, and parities for the normal data and the invalid data.