Memory Page ECC Layout for Low-Overhead Secure Data Storage
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Solution Overview
Problem
Existing data processing devices face challenges in efficiently ensuring safety and security during data storage, particularly in scenarios like vehicle control units, where memory accesses need to be secure and efficient without significant overhead or delay.
Innovation Solution
A data processing device with a memory interface circuit that aggregates error checking code bits and additional redundancy bits within additional data words, allowing for efficient memory access and security mechanisms, including caching and generation of safety and security bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error checking code bits and redundancy bits are stored separately for each data word, then data security and reliability are improved, but memory overhead and access complexity increase
Solution Approach 1:
The patent combines multiple error checking code bits and redundancy bits into shared additional data words that serve multiple data words simultaneously. Instead of dedicating separate protection bits to each data word, the system merges protection resources so that one or more additional data words contain aggregated error checking code bits and redundancy bits that protect multiple data words within the same page, reducing overall memory overhead while maintaining data security
Solution Approach 2:
The additional data words serve multiple functions: they contain error checking code bits for detecting data corruption, redundancy bits for security mechanisms, and can be shared across multiple data words. This multi-functional approach allows a single additional data word to provide protection services to numerous data words, improving efficiency and reducing the total number of protection bits needed in the memory system
2Reliability
If error checking code bits are distributed across multiple additional data words, then data protection coverage is improved, but memory access time and processing delay increase
Solution Approach 1:
The patent merges error checking code bits for multiple data words into consolidated additional data words, allowing the memory interface to retrieve all protection bits for a group of data words in a single memory access operation. This combining approach ensures comprehensive data protection coverage while minimizing memory access time by avoiding multiple separate reads for protection bits
Solution Approach 2:
The error checking code bits and redundancy bits are pre-calculated and stored in the additional data words alongside the data words they protect. This preliminary preparation of protection bits eliminates the need for real-time calculation during memory access operations, reducing processing delay while maintaining full data protection coverage
Data Source
AI summary
According to various embodiments, a data processing device is described, comprising a data processing circuit, a memory, configured to store data in form of multiple pages, each page comprising a plurality of data words, a memory controller and a memory interface circuit, configured to store, for each page, user data in multiple data words of the page and error checking code bits for the multiple data words in one or more additional data words of the page, wherein, for at least some of the multiple additional data words, the error checking code bits are included in the same additional data word.