Memory Page Mapping Optimization via Hash Functions
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Solution Overview
Problem
Current virtual computer systems experience cache thrashing and performance reduction due to repetitive memory paging and excessive data exchanges during memory mapping processes, which are not effectively addressed by existing technologies.
Innovation Solution
The system optimizes memory mapping by storing a set of memory page mappings and using a hash function to facilitate memory mapping and un-mapping, eliminating the need for a memory page table walk, thereby reducing cache thrashing and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory page table walk process is used for memory mapping, then memory mapping functionality is achieved, but cache thrashing and excessive data exchanges occur leading to performance degradation
Solution Approach 1:
The patent pre-computes and stores hash values for memory page mappings during system initialization or when mappings change. This preliminary action eliminates the need for full page table walks during runtime memory mapping operations, thereby preventing cache thrashing and improving performance without sacrificing mapping accuracy
Solution Approach 2:
The patent extracts the essential mapping information by storing only hash values of memory page mappings in a compact data structure. This extraction removes the need to traverse entire page tables during memory mapping operations, reducing data access overhead and eliminating cache thrashing while maintaining the necessary mapping functionality
2Measurement precision
If memory page table walk is performed for each memory access, then accurate memory mapping is achieved, but excessive processing cycles and latency occur
Solution Approach 1:
The patent creates a simplified copy of the mapping information in the form of pre-computed hash values stored in a compact data structure. This copy contains the essential mapping relationships without requiring the full page table structure, enabling fast lookups that maintain accuracy while dramatically reducing processing latency
Solution Approach 2:
The patent performs the computationally intensive page table walk operation in advance, storing only the resulting hash values for later use. This preliminary computation eliminates the need to repeat the full page table traversal during actual memory mapping operations, reducing latency while preserving mapping accuracy
Data Source
AI summary
Various aspects provide for optimizing memory mappings associated with network nodes. For example, a system can include a first network node and a second network node. The first network node generates a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node. The second network node receives the memory page request in response to a determination that the second network node comprises a memory space associated with the memory page request. The first network node also maps a memory page associated with the memory page request based on a set of memory page mappings stored by the first network node.