Memory Page Merging Optimization via Dirty Bit Calculation
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Solution Overview
Problem
Electronic devices face challenges in efficiently managing system resources due to limited hardware and software resources, particularly when performing multiple functions, leading to difficulties in satisfying resource demands and optimizing power usage.
Innovation Solution
The method involves optimizing page merging in memory by using the KSM execution module to exclude pages with low merging probability, performing dirty bit calculations instead of checksums, reusing or disabling management structures, and efficiently distributing calculations between low-speed and high-speed calculation devices to reduce resource usage and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the KSM execution module scans all pages in memory to merge overlapping pages, then memory deduplication effectiveness is improved, but scanning time and computational overhead increase significantly
Solution Approach 1:
The patent segments the memory scanning process by dividing pages into different categories based on their merging probability. The KSM execution module identifies and excludes pages with low merging probability from the scanning process, while focusing scanning resources on pages with high merging probability. This segmentation allows the system to maintain effective memory deduplication while significantly reducing the overall scanning time and computational overhead.
2Measurement precision
If the KSM execution module performs checksum calculation to verify page volatility, then accuracy in identifying mergeable pages is improved, but calculation speed decreases
Solution Approach 1:
The patent replaces the computationally expensive checksum calculation with a simpler and faster dirty bit calculation method. The dirty bit is a lightweight mechanism that can quickly indicate whether a page has been modified, providing sufficient accuracy for identifying mergeable pages without the heavy computational overhead of checksum verification. This substitution maintains adequate page volatility check accuracy while dramatically improving calculation speed.
3Power
If the electronic device uses multiple GPUs to perform calculations, then processing power and performance are improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic GPU scheduling that adapts to device state, application requirements, and sensor information. The system can dynamically allocate and switch between multiple GPUs based on real-time conditions, activating only the necessary processing power required for each task. This dynamic approach allows the electronic device to utilize multiple GPUs for high-performance operations when needed while reducing power consumption by deactivating or using fewer GPUs during lower-demand periods.
Data Source
AI summary
The present disclosure relates to system resource management in a variety of situations. The present disclosure provides a method and an apparatus for reducing memory requirements and improving processing speed when an electronic device performs padding for a particular arithmetic operation on data. To achieve the above objective, a method for operating an electronic device according to the present disclosure comprises the steps of: reading a first portion of data from a first memory; determining a first padding address based on the address of a byte belonging to a boundary region of the data among a plurality of bytes included in the first portion; writing values of the plurality of bytes and a value corresponding to the first padding address to a second memory; and reading a second portion of the data from the first memory.