Memory Page Management With Parallel Page Table Lookup

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Solution Overview

Problem

The growth rate of memory capacity lags behind processor performance, leading to a 30% reduction in memory capacity per processor core every two years, exacerbating the demand for increased storage-to-compute ratios in applications.

Innovation Solution

A memory page management method that includes acquiring a target virtual address, performing a physical address lookup in a translation lookaside buffer, and if the address is not found, conducting a parallel lookup in local and other memory page tables to access data, with data transfer based on usage popularity and kernel threads to optimize memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory capacity is increased to match processor performance growth, then processor performance is improved, but memory capacity per processor core decreases due to the lagging growth rate

Engineering Contradiction:
Improveprocessor performanceVSAvoidmemory capacity per processor core
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The memory system is segmented into local memory (connected to target processor in target node) and other memories (connected to target processor in other nodes). This segmentation allows the system to utilize distributed memory resources across multiple nodes, effectively increasing the total memory capacity available to each processor core without requiring a single large memory module.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The translation lookaside buffer is designed to store mapping relationships for both local memory and other memories, making it a universal address translation mechanism that handles both local and remote memory accesses. This multi-functionality allows the system to manage heterogeneous memory resources uniformly, improving memory efficiency across the distributed system.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If address mapping overhead is reduced by using translation lookaside buffer, then data access speed is improved, but memory management complexity increases

Engineering Contradiction:
Improvedata access speedVSAvoidmemory management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The translation lookaside buffer pre-stores mapping relationships between virtual addresses and physical addresses for both local and other memories. By performing address translation in advance and caching the results, the system reduces the overhead of address mapping during actual data access operations, thereby improving data access speed while managing complexity through pre-computation.

Inventive Principle:
Principle #10Preliminary action

3Speed

If parallel lookup in local and other memory page tables is performed, then data access speed is improved, but system complexity increases

Engineering Contradiction:
Improvedata access speedVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The system merges the lookup operations for local memory page tables and other memory page tables into a single parallel operation. By combining these lookups, the system achieves faster data access through concurrent processing while managing system complexity through unified control mechanisms that coordinate the parallel operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system introduces a new dimension of parallelism by performing lookups in both local and other memory page tables simultaneously, rather than sequentially. This dimensional change from sequential to parallel processing improves data access speed while the complexity is managed through structured coordination of the parallel lookup operations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12554651B2Memory page management method, system, and apparatus, device, and computer non-volatile readable storage medium
Publication Date: 2026.02.17 LANGCHAO ELECTRONIC INFORMATION IND CO LTD
  • US12554651B2 patent drawing
  • US12554651B2 patent drawing
  • US12554651B2 patent drawing

AI summary

A memory page management method, system, and apparatus, a device, and a computer non-volatile readable storage medium are provided. The method includes acquiring a target virtual address of data to be accessed; performing a physical address lookup in a translation lookaside buffer based on the target virtual address; reading target data to be accessed from a physical address to be accessed if the corresponding physical address to be accessed is found in the translation lookaside buffer; and performing a parallel physical address lookup in a plurality of sets of uniformly addressed page tables based on the target virtual address if the physical address to be accessed is not found in the translation lookaside buffer, and reading the target data to be accessed from the physical address to be assessed if the physical address to be accessed is found.