Memory Page Partitioning for Temporal Voltage Shift Error Reduction
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Solution Overview
Problem
Existing memory sub-systems face high bit error rates due to temporal voltage shift (TVS) in memory cells, which is exacerbated by slow charge loss over time and temperature variations, leading to inefficient data retrieval and storage strategies.
Innovation Solution
The implementation of block family-based error avoidance strategies, where memory cells are grouped into block families with similar programming times and temperatures, allowing for selective tracking and application of threshold voltage offsets to minimize TVS, thereby improving read operations by partitioning data into more granular units and associating them with appropriate voltage bins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed without selective partitioning, then programming speed is maintained, but bit error rates increase due to temporal voltage shift
Solution Approach 1:
The patent divides a set of memory pages into multiple partitions based on programming time characteristics. Pages programmed within a threshold time period are grouped together, while pages exceeding the threshold are separated. This segmentation allows different voltage offset calibration strategies to be applied to different partitions, reducing bit error rates caused by temporal voltage shift without requiring complete re-programming of all pages.
Solution Approach 2:
Instead of applying uniform voltage offset calibration to all pages, the patent applies calibration selectively only to partitions that exceed the programming time threshold. This partial action approach reduces the overall calibration overhead while maintaining reliability for the critical pages that are most susceptible to temporal voltage shift effects.
2Reliability
If uniform voltage offset calibration is applied to all pages, then bit error rates are reduced, but processing and storage resources are wasted
Solution Approach 1:
The patent applies different voltage offset calibration qualities to different partitions based on their specific needs. Pages in partitions that exceed the programming time threshold receive full voltage offset calibration, while pages within the threshold period use default calibration. This local quality approach ensures that resources are concentrated on pages that actually need them, reducing overall processing resource consumption while maintaining read operation accuracy for critical pages.
3Reliability
If pages are partitioned by programming time threshold, then temporal voltage shift is minimized, but metadata storage requirements increase
Solution Approach 1:
The patent stores metadata indicators (such as most significant bits of programming time) only for partitions that exceed the programming time threshold, rather than maintaining complete metadata for all pages. This partial metadata storage approach reduces the quantity of stored information while still providing sufficient data to apply appropriate voltage offset calibration to the pages that need it most.
Data Source
AI summary
Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.