Memory Page Refresh for Read Disturb Latency Reduction

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Solution Overview

Problem

Existing memory systems face inefficiencies due to read disturb errors, where reading one memory cell affects nearby cells, leading to unnecessary block-level refresh operations that increase latency.

Innovation Solution

Implementing a memory system that performs refresh operations at a more granular level, such as a page-level or virtual-page-level, to identify and refresh only affected pages rather than entire blocks, thereby reducing unnecessary refresh operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If block-level refresh operations are performed to mitigate read disturb errors, then memory reliability is improved, but memory system latency increases due to unnecessary refresh operations on unaffected pages

Engineering Contradiction:
Improvememory reliabilityVSAvoidmemory system latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the memory block into smaller page-level units and implements error tracking at the page level. Instead of refreshing entire blocks, the system identifies and tracks only the specific pages that have experienced read disturb errors, then performs refresh operations only on those affected pages. This segmentation allows selective refreshing that maintains reliability while reducing unnecessary operations on unaffected pages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by implementing error tracking and refresh operations at the specific page level rather than uniformly across entire blocks. The system monitors and identifies pages with read disturb errors individually, and applies refresh operations only to those specific pages that need them, rather than applying the same operation to all pages in a block. This localized approach optimizes performance by avoiding unnecessary refresh operations on pages without errors.

Inventive Principle:
Principle #3Local quality

2Loss of time

If page-level refresh operations are implemented to reduce unnecessary refresh operations, then memory system latency is improved, but device complexity increases due to error tracking mechanisms

Engineering Contradiction:
Improvememory system latencyVSAvoiderror tracking complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by proactively tracking and recording read disturb errors as they occur during normal read operations. The system maintains error tracking information in metadata associated with pages, allowing it to identify affected pages before refresh operations are needed. This preliminary error tracking enables the system to perform targeted refresh operations only on pages that have actually experienced errors, rather than using conservative block-level refreshing.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If selective page refresh operations are performed based on error detection, then productivity is improved by reducing unnecessary operations, but measurement precision requirements increase for error detection

Engineering Contradiction:
Improvememory operation efficiencyVSAvoiderror detection precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent implements feedback mechanisms by continuously monitoring read operations and detecting read disturb errors in real-time. The system uses error detection circuitry to sense when pages have been affected by read disturb, and this feedback information is stored in metadata for subsequent refresh operations. This feedback loop ensures that refresh operations are triggered only when actual errors are detected, maintaining high productivity while using reliable error detection to guide the selective refresh process.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250341968A1Read disturb management for memory
Publication Date: 2025.11.06 MICRON TECHNOLOGY INC
  • US20250341968A1 patent drawing
  • US20250341968A1 patent drawing
  • US20250341968A1 patent drawing

AI summary

Methods, systems, and devices for read disturb management for memory are described. In some instances, data may be read from a first page of a virtual block of a memory system. If the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. The memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). The memory system may then refresh the pages.