Large Memory Page Segment Remapping for TLB Efficiency
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Solution Overview
Problem
As memory capacities increase in non-uniform memory access (NUMA) systems, the overhead of translation lookaside buffer (TLB) grows, leading to inefficiencies in handling multi-bit data errors, where single-bit errors can be corrected but multi-bit errors cause entire large memory pages to be retired, wasting capacity and causing system instability.
Innovation Solution
The system transparently remaps faulty memory segments to patch memory in SRAM or other devices, allowing continued use of large memory pages by redirecting access to healthy areas, pre-allocating patch memory based on error rates and minimizing interconnect usage by placing patch memory locally when possible.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory page size is increased to reduce TLB overhead, then TLB efficiency is improved, but system reliability deteriorates because multi-bit errors cause entire large pages to be retired
Solution Approach 1:
The patent segments a large memory page into smaller correctable error segments (e.g., 4 KB segments) that can be independently corrected. When an uncorrectable error occurs in one segment, only that segment is retired rather than the entire large page, thus maintaining TLB efficiency while improving reliability through fine-grained error isolation.
Solution Approach 2:
The patent changes the error correction parameter from page-level to segment-level by introducing a segment size parameter (e.g., 4 KB) that is smaller than the memory page size. This allows the system to correct errors at the segment level using ECC codes while maintaining the benefits of large page sizes for TLB efficiency.
2Quantity of substance
If memory capacity is increased to meet demand, then system capacity is improved, but error handling complexity increases leading to premature page retirement
Solution Approach 1:
The patent applies segmentation to divide large memory pages into smaller segments that can be independently managed and corrected. This reduces error handling complexity by isolating errors to specific segments rather than requiring system-wide intervention, enabling the system to handle higher memory capacities more effectively.
Solution Approach 2:
The patent implements self-service error correction where the memory subsystem automatically detects, isolates, and corrects errors in segments using ECC codes and remapping mechanisms without requiring manual intervention or system shutdown, thus managing complexity autonomously.
3Reliability
If single-bit error correction is implemented, then reliability is improved for minor errors, but multi-bit errors still cause entire pages to be retired wasting capacity
Solution Approach 1:
The patent segments memory pages into smaller correctable segments (e.g., 4 KB) that can be independently corrected. When multi-bit errors occur, only the affected segment is retired rather than the entire page, reducing memory capacity loss while maintaining reliability through segment-level error correction.
Solution Approach 2:
The patent applies local quality by treating different segments of a memory page differently - each segment has its own error correction characteristics and can be independently managed. This allows selective retirement of only the faulty segment while keeping the rest of the page operational, optimizing both reliability and capacity utilization.
Data Source
AI summary
A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.