Semiconductor Memory Page Size Controller
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Solution Overview
Problem
Semiconductor memory devices with fixed page sizes are inefficient as they require accessing the entire page even when only a small portion contains data, leading to suboptimal usage of memory resources.
Innovation Solution
A semiconductor device with a page size controller that adjusts page size by decoding bank selection addresses and row addresses to enable specific banks, allowing for flexible page size configuration based on the number of stacked semiconductor chips, enabling efficient data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed page size is used in semiconductor memory, then the device structure is simple and easy to manufacture, but memory resources are inefficiently utilized when only a small portion of a page contains data
Solution Approach 1:
The patent implements dynamic page size adjustment by using a page size controller that can switch between different page sizes (e.g., 1K, 2K, 4K bytes) based on decoded bank selection addresses. This allows the memory system to adapt page size to actual data access patterns, improving memory resource utilization while maintaining manufacturing simplicity through a relatively simple decoder-based control mechanism
Solution Approach 2:
The invention changes the page size parameter dynamically by decoding specific bits of the bank selection address (e.g., using BA<1:0> or BA<2:0>) to select different page sizes. This parameter change is achieved through address decoding logic that activates different bank enable signals, allowing flexible memory access without complex structural modifications
2Ease of operation
If the entire page is accessed to retrieve a small portion of data, then fixed page size access is simple to implement, but access time is increased and power consumption is higher
Solution Approach 1:
The patent enables partial page access by allowing the memory system to access only the necessary portion of memory data rather than the entire fixed page. By dynamically adjusting page size based on address decoding, the system performs partial actions (accessing only needed data portions) which reduces access time and power consumption while maintaining operational simplicity through address-based control
3Adaptability or versatility
If multiple banks are enabled to increase page size, then memory capacity and flexibility are improved, but device complexity and control difficulty increase
Solution Approach 1:
The patent segments the bank selection address into different parts, where specific bits (e.g., BA<1:0> or BA<2:0>) are used to control page size and bank enabling. This segmentation allows independent control of page size and bank selection, managing device complexity by organizing control signals in a structured, hierarchical manner while maintaining high adaptability
Data Source
AI summary
A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.