Memory Page Size Identification Registers for Versatile Processing Systems
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Solution Overview
Problem
Existing processing systems face limitations in dynamically managing memory page sizes, leading to restricted versatility and increased costs due to hardware-dependent implementations and differing CPU architectures, which require custom kernel code for page size support.
Innovation Solution
A processing system with initialization software that identifies supported memory page sizes and stores this information in memory page size identification registers, allowing for variable page size management without direct kernel linkage, enabling efficient isolation and access of supported page sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple page sizes are implemented using hardware with different characteristics, then page size versatility is improved, but system cost increases significantly
Solution Approach 1:
The patent extracts the page size identification functionality from the kernel into separate identification registers (e.g., MSR registers). This allows the kernel to access supported page sizes without being coupled to hardware-specific implementation details, reducing complexity while maintaining versatility across different CPU architectures
Solution Approach 2:
The identification registers serve as a universal interface that works across different CPU architectures and page size implementations. The kernel reads from these standardized registers to determine supported page sizes, making the system adaptable to various hardware configurations without requiring architecture-specific kernel code
2Measurement precision
If page size support is implemented in CPU architecture-specific kernel code, then page size identification accuracy is improved, but development cost and time increase
Solution Approach 1:
The patent introduces identification registers as an intermediary layer between the hardware and the kernel. These registers contain page size support information in a standardized format that the kernel can read universally, eliminating the need for architecture-specific kernel code while maintaining accurate page size identification
Solution Approach 2:
The patent changes the parameter representation of page size support from architecture-specific code structures to standardized register values. Each bit in the identification register corresponds to a specific page size, providing a universal parameter encoding scheme that works across different CPU architectures
3Device complexity
If fixed page sizes are used in the system, then system complexity is reduced, but memory management performance deteriorates
Solution Approach 1:
The patent enables dynamic page size selection by providing the kernel with information about multiple supported page sizes through the identification registers. The kernel can dynamically choose appropriate page sizes based on workload requirements, improving memory management performance while maintaining relatively simple system structures
Data Source
AI summary
A processing system includes initialization software that is executable by a processor to identify one or more memory page sizes supported by the processing system. The supported memory page sizes that are identified by the initialization software are stored in one or more memory page size identification registers. Individual bits of the one or more memory page size identification registers may be respectively associated with a memory page size. Whether a memory page size is supported by the processing system may be determined by checking the logic state of the individual bit corresponding to the memory page size.