Memory Page Versioning for Smart Card Data Integrity

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Solution Overview

Problem

Smart cards and similar devices face challenges in updating nonvolatile memory due to interruptions and disturbances, such as tearing events, which can lead to data corruption and collisions, especially during contactless communication, where power fluctuations and external interferences are common, and existing solutions like progress flags require additional memory and write operations.

Innovation Solution

A method that selects a memory page based on version information, reprograms it without erasing, and maps it to a logical memory page, using a quality read operation to ensure data readability, reducing time overhead and memory allocation for progress flags.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If progress flags are used to track memory update status, then data integrity can be maintained during tearing events, but additional memory allocation and write operations are required

Engineering Contradiction:
Improvedata integrityVSAvoidmemory allocation
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the status tracking function from dedicated progress flag memory locations and integrates it into the existing memory data structure. Version information is embedded within the memory pages themselves rather than requiring separate flag storage, eliminating the need for additional memory allocation while maintaining the ability to track update status and detect tearing events

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The memory pages serve multiple functions: they store both the actual data and the version information simultaneously. This multi-functionality allows the same memory space to fulfill both data storage and status tracking roles, avoiding the need for separate progress flag memory locations and reducing overall memory requirements

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If progress flags are used to track memory update status, then data integrity can be maintained during tearing events, but additional write operations are required

Engineering Contradiction:
Improvedata integrityVSAvoidwrite operations
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the status tracking function from dedicated progress flag memory locations and integrates it into the existing memory data structure. Version information is embedded within the memory pages themselves rather than requiring separate flag storage, eliminating the need for additional memory allocation while maintaining the ability to track update status and detect tearing events

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The memory pages serve multiple functions: they store both the actual data and the version information simultaneously. This multi-functionality allows the same memory space to fulfill both data storage and status tracking roles, avoiding the need for separate progress flag memory locations and reducing overall memory requirements

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If memory pages are erased before reprogramming during updates, then data cleanliness is maintained, but time overhead increases due to additional erase operations

Engineering Contradiction:
Improvedata cleanlinessVSAvoidtime overhead
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by overwriting the memory page with new data directly without performing a prior erase operation. The version information is updated concurrently with the data write, ensuring that the memory page transitions directly to its new state. This eliminates the time-consuming erase step while maintaining data integrity through version tracking

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuity of useful action by keeping the memory page in a usable state throughout the update process. Instead of erasing (which creates a temporary non-functional state), the system continuously writes new data and updates version information, ensuring the memory page remains operational and accessible throughout the update sequence

Inventive Principle:
Principle #20Continuity of useful action

4Reliability

If multiple memory pages point to the same logical memory page, then redundancy is provided against tearing events, but collisions can occur during simultaneous updates

Engineering Contradiction:
ImproveredundancyVSAvoidcollision management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback through version information that is read and compared during the update process. When a memory page is selected for updating, its version information is checked to detect potential collisions. If a collision is detected (indicating simultaneous update attempts), the system can respond by aborting or retrying the operation, thus managing the complexity of multiple pages pointing to the same logical page

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP3226141B1Method for performing data updates
Publication Date: 2021.04.07 NXP BV
  • EP3226141B1 patent drawingFigure 1
  • EP3226141B1 patent drawingFigure 2
  • EP3226141B1 patent drawingFigure 3

AI summary

In accordance with a first aspect of the present disclosure, a method is conceived for resolving collisions resulting from tearing events when updating memory, the method comprising: selecting a memory page from a plurality of memory pages pointing to a logical memory page based on version information; re-programming the selected memory page; and mapping the selected memory page to the logical memory page. In accordance with a second aspect of the present disclosure, a corresponding non-transitory computer-readable storage medium comprising instructions is provided. In accordance with a third aspect of the present disclosure, a corresponding integrated circuit is provided.