Semiconductor Memory Paired Transistors Reduce RC Delay
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Solution Overview
Problem
In semiconductor memory devices like DRAM and SRAM, signal transmission over long distances results in significant RC delays due to charge loss through word and bit lines, inhibiting high-speed operation.
Innovation Solution
The use of paired transistors operating in a differential manner, formed in the same well region, allows for charge exchange between transistors, reducing capacitance and enabling high-speed signal transmission by reutilizing charge, thereby minimizing RC delays and enhancing operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional transistor switching is used in semiconductor memory devices, then the device can operate, but RC delays in word lines and bit lines significantly limit the operation speed
Solution Approach 1:
The patent merges the functions of charge pumping and charge storage by forming paired transistors in the same well region. The first transistor pumps charge onto the bit line, while the second transistor simultaneously pumps charge from the bit line, creating a differential charge pumping mechanism that reduces RC delays and enables high-speed operation.
Solution Approach 2:
The paired transistors in the same well region act as intermediaries that facilitate charge exchange between the bit line and the well region. This intermediary mechanism allows for efficient charge pumping that overcomes the RC delay limitation in conventional transistor switching.
2Speed
If charge is pumped up and down for transistor state transition, then high speed switching is achieved, but additional circuits are required increasing device complexity
Solution Approach 1:
The patent combines the charge pumping function with the transistor structure itself by forming paired transistors in the same well region. This integration eliminates the need for separate auxiliary charge pumping circuits, achieving high-speed switching without increasing device complexity.
Solution Approach 2:
The paired transistors in the same well region serve themselves by utilizing the well region as a common charge reservoir. The first transistor pumps charge onto the bit line while the second transistor simultaneously pumps charge from the bit line, creating a self-sustaining differential charge pumping mechanism without external assistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high-speed operation with reduced capacitance, allowing for efficient signal transmission and low power consumption, eliminating the need for auxiliary circuits and minimizing RF delays, while maintaining high sensitivity and sensing capability.
Implementation Method 1
paired transistors being formed in a same well region so as to be adjacent to each other, and operating in a differential manner
Implementation Method 2
reducing capacitance and enabling high-speed signal transmission by reutilizing charge
Implementation Method 3
When a line such as the word line or bit line is regarded as a transmission line, this line is released from the RC delay, and a signal delay is obtained as only a delay caused by an electromagnetic wave speed
Data Source
AI summary
A memory cell MC includes nMOS transistors for a transfer gate configured to be paired with each other, and one capacitor for data storage connected to the nMOS transistor. A gate electrode of the nMOS transistor is connected to a word line WL, and a drain is connected to a bit line BL. A gate electrode of the nMOS transistor is connected to a word line /WL, and a drain and a source are connected to a ground. The capacitor is connected between a source of the nMOS transistor and the ground. A Y selector circuit is connected between a differential bit line BL, /BL and a differential data line DL, /DL. The Y selector circuit has two pairs of nMOS transistors configured to be paired transistors, respectively.