Memory DQ Signal Scaling With PAM for High-Speed Low-Power Transfer
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Solution Overview
Problem
Current memory systems face challenges in achieving high-capacity and high-speed data transmission using non-return to zero (NRZ) type encodings, necessitating the exploration of alternative signal processing methods like pulse amplitude modulation (PAM) to enhance data transmission performance and reduce power consumption.
Innovation Solution
The implementation of a memory device and system that employs n-level pulse amplitude modulation (PAMn) for DQ signal transmission/reception, scaling the DQ signal based on operating frequency conditions to optimize data transmission performance and power consumption, by adjusting the interval between adjacent levels and transition slope of the DQ signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-return to zero (NRZ) type encodings are used for data transmission, then the implementation is simple, but high-capacity and high-speed data transmission demands cannot be satisfied
Solution Approach 1:
The patent applies pulse amplitude modulation (PAM) with n-level modulation (n≥4) to change the signal parameters from traditional NRZ binary levels to multiple amplitude levels. This allows more data bits to be transmitted per signal cycle, directly increasing data transmission capacity and speed while managing complexity through structured modulation schemes
2Productivity
If high-capacity data transmission is implemented using PAM methods, then data transmission performance improves, but power consumption increases
Solution Approach 1:
The patent dynamically adjusts the DQ signal parameters including the interval between adjacent PAM levels and transition slopes based on operating frequency conditions. At lower frequencies, the system reduces signal amplitude variations and transition speeds, thereby lowering power consumption while maintaining adequate data transmission capacity. This dynamic adaptation allows the system to optimize the trade-off between data capacity and power usage across different operating conditions
3Reliability
If fixed DQ signal parameters are used, then the circuit design is simple, but data transmission performance degrades under varying frequency conditions
Solution Approach 1:
The patent implements dynamic scaling of DQ signal parameters based on detected operating frequency conditions. The system adjusts the interval between adjacent PAM levels and transition slopes according to the actual operating frequency, ensuring optimal signal characteristics across different frequency ranges. This dynamic parameter adjustment maintains reliable data transmission performance while adapting to varying operational requirements
Solution Approach 2:
The patent incorporates frequency detection and feedback mechanisms that monitor the operating frequency condition and use this information to adjust DQ signal parameters accordingly. The system measures the actual operating frequency and feeds this information back to the signal generation circuitry, which then modifies the PAM level intervals and transition slopes to match the detected frequency conditions, ensuring consistent transmission performance
Data Source
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AI summary
A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.