Semiconductor Memory Parallel Block Programming
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Solution Overview
Problem
Current NAND flash memory devices face inefficiencies in test mode writing, leading to longer test times and increased production costs due to sequential writing across blocks, and high verify current consumption during concurrent verification across multiple blocks.
Innovation Solution
Incorporation of a multi-block selection circuit that allows parallel writing on multiple blocks while performing verification only on a singular block, reducing test time and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential writing is performed across all blocks in test mode, then verification can be completed, but test time increases significantly
Solution Approach 1:
The memory device is divided into multiple blocks, and the test mode writing operation is segmented such that multiple blocks can be processed in parallel. The controller selectively performs parallel programming on multiple blocks while performing verification only on a singular block, thereby reducing overall test time while maintaining verification completeness.
2Loss of time
If concurrent verification is performed across multiple blocks, then test time is reduced, but verify current consumption becomes excessively high
Solution Approach 1:
Different blocks are treated differently during test mode: some blocks are selected for parallel programming while only one block is selected for verification. This local differentiation ensures that verification current consumption is controlled to acceptable levels while still achieving time reduction through parallel processing of multiple blocks.
3Productivity
If parallel writing is performed on multiple blocks, then productivity increases, but control complexity increases
Solution Approach 1:
The controller is designed with multi-functionality to handle both parallel programming and selective verification operations. It can identify target blocks for parallel programming, select a singular block for verification, and coordinate the overall test mode operation, thereby achieving high productivity without excessive control complexity.
Data Source
AI summary
According to one embodiment, a semiconductor memory device comprises a first memory cell array including a first block and a second block, the first block including a first memory cell, and the second block including a second memory cell; and a controller that performs, in a first period of time in writing, a first program in the first memory cell and the second memory cell.