Memory Error Recovery Using Parallel Chipkill Decoding
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Solution Overview
Problem
In memory systems, existing error correction methods often lead to increased latency and resource consumption due to sequential processing of errors, which can degrade data input/output performance and operational reliability.
Innovation Solution
The implementation of a method that allows parallel error recovery operations, including chipkill decoding, to correct multi-bit errors by reading neighboring data segments and adjusting read voltage based on decoding results, thereby reducing latency and resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential error correction processing is used, then error correction can be completed with simple processing steps, but latency increases and data input/output performance deteriorates
Solution Approach 1:
The system performs preliminary actions by preparing multiple candidate correction results in advance through parallel processing paths. Multiple decoding operations are initiated simultaneously, and the valid correction result is selected afterward, thereby reducing the time for error correction while maintaining manageable processing complexity.
Solution Approach 2:
The system dynamically switches between different error correction processing paths based on the type of error detected. For single-bit errors, a simple correction path is used, while for multi-bit errors, a more complex parallel processing path is activated. This dynamic adaptation optimizes both latency and processing complexity for different error scenarios.
2Use of energy by moving object
If sequential error correction processing is used, then resource consumption can be controlled, but data input/output performance and operational reliability deteriorate
Solution Approach 1:
Multiple candidate correction results are prepared in advance through parallel processing, so that when an error is detected, the system can quickly select from pre-computed results rather than performing sequential corrections. This improves data input/output performance while the system manages resource consumption by selectively activating parallel paths only when needed.
Solution Approach 2:
The system changes processing parameters dynamically based on error detection results. When single-bit errors are detected, a low-resource correction path is used. When multi-bit errors are detected, the system transitions to a higher-resource parallel processing path, optimizing the balance between resource consumption and productivity for different error conditions.
3Device complexity
If traditional error correction methods are used, then processing simplicity is maintained, but operational reliability decreases due to increased latency
Solution Approach 1:
The system performs preliminary parallel decoding operations to generate multiple candidate correction results before final selection. This approach maintains processing simplicity from the user perspective while internally executing complex parallel operations that improve operational reliability by reducing latency and providing multiple validation paths.
Solution Approach 2:
The system uses feedback mechanisms to validate correction results. Multiple decoding paths generate candidate results that are then verified against checksum or parity information. This feedback loop ensures operational reliability by confirming the correctness of error corrections while maintaining a relatively simple overall processing structure.
Data Source
AI summary
A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable.